Method for manufacturing a planar, self-aligned emitter-base complex

Claim 1

A method for the manufacture of a planar, self-aligned emitter-base complex including a substrate of semiconductor material, a semiconductor layer structure for hetero-bipolar transistors that is grown thereon, whereby at least one semiconductor layer is doped for the conductivity type of the base, including a passivation layer, including base metallization and a portion of a first dielectric layer situated thereon, and including emitter metallization and a portion of a second dielectric layer situated thereon, the method utilizing phototechnique and lift-off technique, etching technique, implantation and tempering processes, comprising the steps of: (a) proceeding from the substrate having the semiconductor layer structure grown thereon, a passivation layer is deposited surface-wide on the uppermost of the semiconductor layers; (b) a first mask layer having an opening for the definition of the base is applied; (c) an implantation of doping for the conductivity type of the base proceeds first for the formation of a implantated base region through the passivation layer at least down to the semiconductor layer doped for the conductivity type of the base; (d) the passivation layer and the uppermost semiconductor layer are etched away in those regions occupied by the opening of the first mask layer that serves the purpose of defining the base; (e) a first metal layer including a first portion as base metallization and having a second portion is applied on the first mask layer; (f) a high-temperature resistant metal is used as the first metal layer allowing the base metallization to not be negatively influenced by a subsequent tempering cycle for annealing the implantation; (g) a first dielectric layer having a first portion on the base metallization and having a second portion on the second portion of the first metal layer is deposited; (h) the first mask layer together with the second portion of the first metal layer and the second portion of the first dielectric layer are removed in a lift-off technique; (i) a temperature-time cycle is carried out with which the implanted dopant is annealed and the base metallization is alloyed in at the same time; (j) a second dielectric layer is isotropically deposited; (k) the second dielectric layer and the passivation layer are etched away to such an extent with anisotropic etching that only spacers completely covering the sides of the base metallization remain; (l) a second mask layer for the definition of the emitter is applied; (m) a second metal layer having a first portion as emitter metallization and having a second portion is applied on the second mask layer; (n) a third dielectric layer having a first portion on the emitter metallization and a second portion on the second portion of the second metal layer is applied; (o) the second mask layer together with the second portion of the second metal layer and the second portion of the third dielectric layer are removed in a lift-off technique; (p) the emitter metallization is alloyed in; (q) the exposed portions of the uppermost semiconductor layer are etched away; and (r) those portions of the semiconductor layer structure situated outside of the regions of the surface occupied by emitter and base are rendered insulating by insulation implantation at that side facing away from the substrate down to and including the semiconductor layer doped for the conductivity type of the base.

Claim 2

A method for the manufacture of a planar, self-aligned emitter-base complex including a substrate of semiconductor material, a semiconductor layer structure for hetero-bipolar transistors that is grown thereon, whereby at least one semiconductor layer is doped for the conductivity type of the base, including a passivation layer, including base metallization and a portion of a first dielectric layer situated thereon, and including emitter metallization and a portion of a second dielectric layer situated thereon, the method utilizing phototechnique and lift-off technique, etching technique, implantation and tempering processes, comprising the steps of: (a) proceeding from the substrate having the semiconductor layer structure grown thereon, a passivation layer is deposited surface-wide on the uppermost of the semiconductor layers; (b) a first mask layer having an opening for the definition of the base is applied; (c) an implantation of doping for the conductivity type of the base proceeds first for the formation of a implantated base region through the passivation layer at least down to the semiconductor layer doped for the conductivity type of the base; (d) the passivation layer and the uppermost semiconductor layer are etched away in those regions occupied by the opening of the first mask layer that serves the purpose of defining the base; (e) a first metal layer including a first portion as base metallization and having a second portion is applied on the first mask layer; (f) a high-temperature resistant metal is used as the first metal layer allowing the base metallization to not be negatively influenced by a subsequent tempering cycle for annealing the implantation; (g) a first dielectric layer having a first portion on the base metallization and having a second portion on the second portion of the first metal layer is deposited; (h) the first mask layer together with the second portion of the first metal layer and the second portion of the first dielectric layer are removed in a lift-off technique; (i) a temperature-time cycle is carried out with which the implanted dopant is annealed and the base metallization is alloyed in at the same time; (j) a second dielectric layer is isotropically deposited; (k) the second dielectric layer and the passivation layer are etched away to such an extent with anisotropic etching that only spacers completely covering the sides of the base metallization remain; (l) a second mask layer for the definition of the emitter is applied; (m) a second metal layer having a first portion as emitter metallization and having a second portion is applied on the second mask layer; (n) a third dielectric layer having a first portion on the emitter metallization and a second portion on the second portion of the second metal layer is applied; (o) the second mask layer together with the second portion of the second metal layer and the second portion of the third dielectric layer are removed in a lift-off technique; (p) the emitter metallization is alloyed in; (q) the exposed portions of the uppermost semiconductor layer are etched away; and (r) those portions of the semiconductor layer structure situated outside of the regions of the surface occupied by emitter and base are rendered insulating by insulation implantation at that side facing away from the substrate down to and including the semiconductor layer doped for the conductivity type of the base.

Claim 12

A method for the manufacture of a planar, self-aligned emitter-base complex including a substrate of semiconductor material, a semiconductor layer structure for hetero bipolar transistors that is grown thereon, whereby at least one semiconductor layer is doped for the conductivity type of the base, including a passivation layer, including base metallization and a portion of a first dielectric layer situated thereon, and including emitter metallization and a portion of a second dielectric layer situated thereon, the method utilizing phototechnique, lift-off technique, etching technique, implantation and tempering processes, comprising the steps of: (a) proceeding from the substrate having the semiconductor layer structure grown thereon, a passivation layer is deposited surface-wide on the uppermost of these semiconductor layers; (b) a first mask layer including an opening for the definition of the base is applied; (c) an implantation of doping for the conductivity type of the base proceeds first for the formation of implanted base region through the passivation layer at least down to the semiconductor layer doped for the conductivity type of the base; (d) the passivation layer and the uppermost semiconductor layer are etched away in the regions occupied by the opening of the first mask layer serving for the definition of the base; (e) a first metal layer having a first portion as base metallization and having a second portion on the first mask layer is applied; (f) a high-temperature resistant metal is used for this first metal layer, allowing the base metallization is not be negatively influenced by a following tempering cycle for annealing the doping; (g) a first dielectric layer having a first portion on the base metallization and having a second portion on the second portion of the first metal layer is deposited; (h) the first mask layer together with the second portion of the first dielectric layer are removed in lift-off technique; (i) a temperature-time cycle is performed with which the implanted doping is annealed and the base metallization is alloyed in at the same time; (j) a second dielectric layer is isotropically deposited; (k) the second dielectric layer and the passivation layer are etched away to such an extent with anisotropic etching that only spacers completely covering the sides of the base metallization remain; (l) a second metal layer is deposited onto the surface comprising the base metallization; (m) a third dielectric layer is deposited on the second metal layer; (n) a second mask layer is applied for the definition of the emitter; (o) those parts of the second metal layer and of the third dielectric layer not covered by the second mask layer are etched away with anisotropic etching, so that only the emitter metallization of this second metal layer remains; (p) the second mask layer is removed; (q) the emitter metallization is alloyed in; (r) the exposed portions of the uppermost semiconductor layer are etched away; and (s) those portions of the semiconductor layer structure situated outside of the regions of the surface occupied by base and emitter are rendered insulating by insulation implantation at that side facing away from the substrate down to and including the semiconductor layer doped for the conductivity type of the base.

Claim 13

A method for the manufacture of a planar, self-aligned emitter-base complex including a substrate of semiconductor material, a semiconductor layer structure for hetero bipolar transistors that is grown thereon, whereby at least one semiconductor layer is doped for the conductivity type of the base, including a passivation layer, including base metallization and a portion of a first dielectric layer situated thereon, and including emitter metallization and a portion of a second dielectric layer situated thereon, the method utilizing phototechnique, lift-off technique, etching technique, implantation and tempering processes, comprising the steps of: (a) proceeding from the substrate having the semiconductor layer structure grown thereon, a passivation layer is deposited surface-wide on the uppermost of these semiconductor layers; (b) a first mask layer including an opening for the definition of the base is applied; (c) an implantation of doping for the conductivity type of the base proceeds first for the formation of implanted base region through the passivation layer at least down to the semiconductor layer doped for the conductivity type of the base; (d) the passivation layer and the uppermost semiconductor layer are etched away in the regions occupied by the opening of the first mask layer serving for the definition of the base; (e) a first metal layer having a first portion as base metallization and having a second portion on the first mask layer is applied; (f) a high-temperature resistant metal is used for this first metal layer, allowing the base metallization is not be negatively influenced by a following tempering cycle for annealing the doping; (g) a first dielectric layer having a first portion on the base metallization and having a second portion on the second portion of the first metal layer is deposited; (h) the first mask layer together with the second portion of the first dielectric layer are removed in lift-off technique; (i) a temperature-time cycle is performed with which the implanted doping is annealed and the base metallization is alloyed in at the same time; (j) a second dielectric layer is isotropically deposited; (k) the second dielectric layer and the passivation layer are etched away to such an extent with anisotropic etching that only spacers completely covering the sides of the base metallization remain; (l) a second metal layer is deposited onto the surface comprising the base metallization; (m) a third dielectric layer is deposited on the second metal layer; (n) a second mask layer is applied for the definition of the emitter; (o) those parts of the second metal layer and of the third dielectric layer not covered by the second mask layer are etched away with anisotropic etching, so that only the emitter metallization of this second metal layer remains; (p) the second mask layer is removed; (q) the emitter metallization is alloyed in; (r) the exposed portions of the uppermost semiconductor layer are etched away; and (s) those portions of the semiconductor layer structure situated outside of the regions of the surface occupied by base and emitter are rendered insulating by insulation implantation at that side facing away from the substrate down to and including the semiconductor layer doped for the conductivity type of the base.