Stack with unary encoded stack pointer

Claim 2

A memory stack comprising: a plurality of multi-bit storage elements for storing data in fixed positions as a stack; I/O bus means coupled to each of said storage elements; a plurality of control means for enabling the input and output of data, each being coupled between said I/O bus means and a single one of said storage elements; and an unary encoded stack pointer consisting of a serial, bidirectional shift register having a plurality of single bit outputs, each single bit output being coupled to a single one of said control means, such that a value having a single active bit can be shifted in said shift register to point to a one of said storage elements which is a top of said stack.

Claim 3

The memory stack of claim 1 wherein said I/O bus means includes an input bus coupled to the inputs of said multi-bit storage elements and an output bus coupled to the outputs of said multi-bit storage elements, and said plurality of control means includes first means for enabling a load control of said storage elements responsive to said shift register outputs, a plurality of output drivers coupling said storage elements to said output bus, and second means for enabling a drive control of said output drivers responsive to said shift register outputs.

Claim 4

The memory stack of claim 2 wherein said first and second means for enabling each comprises a series of NAND or AND gates.

Claim 5

The memory stack of claim 3 wherein one input of each of said NAND or AND gates is coupled to an output of said shift register and further comprising: a push enable line coupled to a second input of said NAND or AND gates for said first means for enabling; and a pop enable line coupled to a second input of each NAND or AND gate of said second means for enabling.

Claim 6

The memory stack of claim 1 further comprising means for loading a constant into said shift register, said constant being a digital number with a single digital one.

Claim 7

The memory stack of claim 1 wherein said first-mentioned serial shift register has each output coupled to a load control input of one of said multi-bit storage elements, and further comprising a second serial shift register having a plurality of single bit outputs, each single bit output of said second shift register being coupled to a driver control for an output of one of said multi-bit storage elements.

Claim 8

A memory stack comprising: a plurality of multi-bit storage elements; and a serial shift register having a plurality of single bit outputs; an input bus coupled to the inputs of said multi-bit storage elements; an output bus coupled to the outputs of said multi-bit storage elements; first means for enabling a load control of said storage elements including a series of NAND or AND gates, one input of each NAND or AND gate being coupled to one of said shift register outputs; a plurality of output drivers coupling said storage elements to said output bus; second means for enabling a drive control of said output drivers including a series of AND gates, one input of each NAND or AND or NAND gate being coupled to one of said shift register outputs; a push enable line coupled to a second input of said NAND or AND gates for said first means for enabling; a pop enable line coupled to a second input of each NAND or AND gate of said second means for enabling; and means for loading a constant into said shift register, said constant being a digital number with a single digital one.

Claim 9

A memory stack comprising: a plurality of multi-bit storage elements; and a serial shift register having a plurality of single bit outputs; an input bus coupled to the inputs of said multi-bit storage elements; an output bus coupled to the outputs of said multi-bit storage elements; first means for enabling a load control of said storage elements including a series of NAND or AND gates, one input of each NAND or AND gate being coupled to one of said shift register outputs; a plurality of output drivers coupling said storage elements to said output bus; second means for enabling a drive control of said output drivers including a series of AND gates, one input of each NAND or AND or NAND gate being coupled to one of said shift register outputs; a push enable line coupled to a second input of said NAND or AND gates for said first means for enabling; a pop enable line coupled to a second input of each NAND or AND gate of said second means for enabling; and means for loading a constant into said shift register, said constant being a digital number with a single digital one.