US4152778A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital computer memory
Assignee: Raytheon Co
•
Filing: 1976-09-30
•
Granted: 1979-05-01
•
Expires: 1996-09-30
Abstract
Abstract A digital computer memory made up of a plurality of read only memory components arranged in a matrix of rows and columns. The outputs of the columns of memory components are connected to a voltage source and load resistors to provide the output terminals of the memory. Sets of digital words having at least a field or portion of a field with bits represented by the same logical state are grouped in such memory so that, when a word in such set is addressed, the bits in such field are produced at the output terminals by the volage source and load resistors. With such arrangement the number of read only memory components required in such memory is reduced.
Inventors
- 👤 Stanley M. Nissen
- 👤 Steven J. Wallach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:30
CPC Classifications
G; G11; G11C; G11C17/00; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
201 words
A digital computer memory comprising: (a) a plurality of data storage components arranged in a matrix of rows and columns, each one of such components comprising: (i) a set of address terminals; (ii) a plurality of bits of storage at each one of a plurality of locations; (iii) a set of component output terminals; and, (iv) a set of gates, each component output terminal in such set being fed by one of such gates, such gate being responsive to component enable/disable signals, for allowing a voltage source to produce a logical signal at such output terminal in response to the disable signal and for coupling to such output terminal in response to the enable signal a corresponding one of the stored bits in the location addressed by data applied to the set of address terminals producing a logical signal at such output terminal in accordance with the stored bit; (b) means for coupling the component output terminals of the columns of data storage components to a corresponding one of a plurality of memory output terminals; and (c) wherein the number of data storage components in one row thereof is different from the number of data storage components in another row thereof.
Claim 2
Dependent Claim
201 words
A digital computer memory comprising: (a) a plurality of data storage components arranged in a matrix of rows and columns, each one of such components comprising: (i) a set of address terminals; (ii) a plurality of bits of storage at each one of a plurality of locations; (iii) a set of component output terminals; and, (iv) a set of gates, each component output terminal in such set being fed by one of such gates, such gate being responsive to component enable/disable signals, for allowing a voltage source to produce a logical signal at such output terminal in response to the disable signal and for coupling to such output terminal in response to the enable signal a corresponding one of the stored bits in the location addressed by data applied to the set of address terminals producing a logical signal at such output terminal in accordance with the stored bit; (b) means for coupling the component output terminals of the columns of data storage components to a corresponding one of a plurality of memory output terminals; and (c) wherein the number of data storage components in one row thereof is different from the number of data storage components in another row thereof.
Claim 3
Dependent Claim
16 words
The digital computer memory recited in claim 1 wherein the data storage components are memory components.
Claim 4
Dependent Claim
29 words
The digital computer memory recited in claim 2 wherein the component output terminals in the columns of data storage components are wired -OR to output terminals of the memory.
References Cited (Backward Citations)
US3560940A
Cited
US3644906A
Cited
US3772658A
Cited
US3763480A
Cited
US3781826A
Cited
US3863232A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-30 | 1982-10-30 | 1983-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-30 | 1986-10-30 | 1987-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-30 | 1990-10-30 | 1991-05-01 | $7700.00 | Window Closed / Lapsed |