Associative array

Claim 2

An associative array including: a plurality of memory cells arranged in rows and columns; some of said rows of said memory cells forming rows of storage cells with said storage cells of each row being a word; the remainder of said rows of said cells forming rows of read cells, the number of said rows of said read cells being onehalf the number of said rows of said storage cells; each of said storage cells being formed by said memory cells in two adjacent columns; each of said read cells being formed by one of said memory cells; each of said rows of said read cells providing outputs for two of said rows of said storage cells; said two rows of said storage cells and said row of said read cells providing outputs for said two rows of said storage cells being adjacent each other; first means to connect one of said adjacent rows of said storage cells to one-half of said read cells in said adjacent row of said read cells with said connected read cells being in odd columns; second means to connect the other of said adjacent rows of said storage cells to the other half of said read calls in said adjacent row of said read cells with said connected read cells being in even columns; said storage cells of said one adjacent row transmitting a signal through said first connecting means to said connected read cells when an address to all of said rows of said storage cells selects the word of said one adjacent row to cause said connected read cells to provide an output; and said storage cells of said other adjacent row transmitting a signal through said second connecting means to said connected read cells when an address to all of said rows of said storage cells selects the word of said other adjacent row to cause said connected read cells to provide an output.

Claim 3

The array according to claim 1 including means connecting the output of one of said read cells for each of said rows of said storage cells to each other to produce an output when the addressed word is in at least one of said rows of said storage cells.

Claim 4

The array according to claim 2 in which: said storage cell in the two adjacent columns in each of said rows and said cells in the same two adjacent columns in each of said rows has a common bit line; one of said memory cells of each of said storage cells and each of said read cells in one of the two adjacent columns is connected to a second common bit line; and the other of said memory cells of each of said storage cells and each of said read cells in the other of the two adjacent columns is connected to a third common bit line.

Claim 5

The array according to claim 3 in which each of said first and second connecting means comprises a first line connected to one of said memory cells of each of said storage cells in each of said rows in one of the two adjacent columns connected to a common bit line and a second line connected to the other of said memory cells of each of said storage cells in each of said rows in the other of the two adjacent columns connected to the common bit line.

Claim 6

The array according to claim 2 in which said memory cell of each of said storage cells and each of said read cells in the same column are connected to the same two bit lines.

Claim 7

The array according to claim 1 in which said rows of said storage cells and said read cells are arranged with two of said rows of said read cells adjacent each other and having four of said rows of said storage cells above and below except that the uppermost two of said rows of said read cells have only two of said rows of said storage cells thereabove and the lowermost two of said rows of said read cells have only two of said rows of said storage cells therebeneath.

Claim 8

The array according to claim 6 in which: a common power distribution line extends between each two adjacent rows of said storage cells to supply a current to each of said memory cells in each of said two adjacent rows; and a common power distribution line extends between each two adjacent rows of said read cells to supply a current to each of said read cells in each of said two adjacent rows.

Claim 9

The array according to claim 1 in which: said storage cell in the two adjacent columns in each of said rows and said read cells in the same two adjacent columns in each of said rows has a common bit line; one of said memory cells of each of said storage cells and each of said read cells in one of the two adjacent columns is connected to a second common bit line; and the other of said memory cells of each of said storage cells and each of said read cells in the other of the two adjacent columns is connected to a third common bit line.

Claim 10

The array according to claim 1 in which said memory cell of each of said storage cells and each of said read cells in the same column are connected to the same two bit lines.

Claim 11

The array according to claim 1 in which: each of said memory cells forming said storage cells includes: a pair of transistors; each of said transistors having a first output electrode, a second output electrode, and a control electrode; means cross coupling the first output electrode of each of said transistors to the control electrode of the other of said transistors whereby said pair of transistors forms a bistable circuit; a separate constant current source connected to the first output electrode of each of said pair of transistors; and a third transistor having a first output electrode, a second output electrode, and a control electrode; a word line connected with at least the odd or even columns of said memory cells in one of the rows of said memory cells forming said storage cells; each of said word lines having a potential thereon; each of said first connecting means inCluding at least one of said word lines; each of said second connecting means including at least one of said word lines; each of said transistors of said pair of transistors of each of said memory cells having its second output electrode connected to one of said word lines; a plurality of search lines with each associated with a column of said memory cells forming said storage cells; each of said search lines being connected to the control electrode of each of said third transistors of said memory cells forming said storage cells in the column; said third transistor having its first output electrode connected to the second output electrode of one of said pair of transistors; said third transistor having its second output electrode connected to a negative voltage line; said third transistor being conductive when said search line has its potential raised and said one transistor is saturated to reduce the potential on said connected word line, said third transistor not being conductive when said search line has its potential raised and the other of said pair of transistors is saturated to not affect the potential on said connected word line; and said read cells connected to said memory cells in each row of said storage cells through one of said first and second connecting means producing the output when the potential on any of said word lines connected to said memory cells in the same row of said storage cells is not reduced.

Claim 12

The array according to claim 1 in which: each of said memory cells forming said read cells includes: a pair of transistors; each of said transistors having a first output electrode, a second output electrode, and a control electrode; means cross coupling the first output electrode of each of said transistors to the control electrode of the other of said transistors whereby said pair of transistors forms a bistable circuit; a separate constant current source connected to the first output electrode of each of said pair of transistors; and a third transistor having a first output electrode, a second output electrode, and a control electrode; a plurality of read word lines; each of said read word lines being connected with said read cells in only the odd or even columns of one of the rows of said read cells; each of said transistors of said pair of transistors having the second output electrode connected to said read word line; a plurality of read lines with each associated with two adjacent columns of said read cells; each of said read lines being connected to the first output electrode of each of said third transistors of said read cells in the two adjacent columns; said thrid transistor having its control electrode connected to the second output electrode of one of said pair of transistors; said third transistors having its second output electrode connected to a negative voltage line; each of said read word lines being connected to a source of potential that decreases when said connected read cells are not to produce an output on said read lines; and said third transistor being conductive when the potential of said read word line is not reduced to produce a potential on said read line, the magnitude of the potential produced on said read line being higher when one of said transistors of said pair of transistors is saturated than when the other of said transistors of said pair of transistors is saturated so as to indicate the state of said read cell in accordance with which of said pair of transistors is saturated.

Claim 13

An associative array having: memory cells arranged in rows and columns, a storage cell being formed by said memory cells in two adjacent columns in the same row; each of said memory cells including: a pair of transistors; each of said transistors having a firs output electrode, a second output electrode, and a control electrode; means cross coupling the first output electrode of each of sAid transistors to the control electrode of the other of said transistors whereby said pair of transistors forms a bistable circuit; a separate constant current source connected to the first output electrode of each of said pair of transistors; and a third transistor having a first output electrode, a second output electrode, and a control electrode; a plurality of word lines, each od said word lines having a potential thereon; each of said word lines being connected with said memory cells in one of the rows of said memory cells and with at least the odd or even columns of said memory cells of the row; each of said transistors of said pair of transistors having its second output electrode connected to said word line; a plurality of search lines with each associated with a column of said memory cells; each of said search lines being connected to the control electrode of each of said third transistors of said memory cells in the column; said third transistor having its first output electrode connected to the second output electrode of one of said pair of transistors; said third transistor having its second output electrode connected to a negative voltage line; said third transistor being conductive when said connected search line has its potential raised and said one transistor of said pair of transistors is saturated to reduce the potential on said connected word line, said third transistor not being conductive when said connected search line has its potnetial raised and the other of said pair of transistors is saturated to not affect the potential on said connected word line; and separate means connected to said memory cells in eachrow through any of said word lines connected to said memory cells in the same row to produce an output when the potential on any of said word lines connected to said memory cells in the same row is not reduced.

Claim 14

An associative array having: memory cells arranged in rows and columns, a storage cell being formed by said memory cells in two adjacent columns in the same row; each of said memory cells including: a pair of transistors; each of said transistors having a firs output electrode, a second output electrode, and a control electrode; means cross coupling the first output electrode of each of sAid transistors to the control electrode of the other of said transistors whereby said pair of transistors forms a bistable circuit; a separate constant current source connected to the first output electrode of each of said pair of transistors; and a third transistor having a first output electrode, a second output electrode, and a control electrode; a plurality of word lines, each od said word lines having a potential thereon; each of said word lines being connected with said memory cells in one of the rows of said memory cells and with at least the odd or even columns of said memory cells of the row; each of said transistors of said pair of transistors having its second output electrode connected to said word line; a plurality of search lines with each associated with a column of said memory cells; each of said search lines being connected to the control electrode of each of said third transistors of said memory cells in the column; said third transistor having its first output electrode connected to the second output electrode of one of said pair of transistors; said third transistor having its second output electrode connected to a negative voltage line; said third transistor being conductive when said connected search line has its potential raised and said one transistor of said pair of transistors is saturated to reduce the potential on said connected word line, said third transistor not being conductive when said connected search line has its potnetial raised and the other of said pair of transistors is saturated to not affect the potential on said connected word line; and separate means connected to said memory cells in eachrow through any of said word lines connected to said memory cells in the same row to produce an output when the potential on any of said word lines connected to said memory cells in the same row is not reduced.

Claim 15

The array according to claim 12 in which: said separate means includes memory cells arranged in rows and columns, a read cell being formed by each of said memory cells; each of read cells includes: a pair of transistors; each of said transistors having a first output electrode, a second output electrode, and a control electrode; means cross coupling the first output electrode of each of said transistors to the control electrode of the other of said transistors whereby said pair of transistors forms a bistable circuit; a separate constant current source connected to the first output electrode of each of said pair of transistors; and a third transistor having a first output electrode, a second output electrode, and a control electrode; a plurality of read word lines; each of said read word lines being connected with said read cells in one of the rows of said read cells; each of said transistors of said pair of transistors of said read cells having the second output electrode connected to one of said read word lines; a plurality of read lines with each associated with at least one column of said read cells; each of said read lines being connected to the first output electrode of each of said third transistors of said read cells in at least the one column; said third transistor having its control electrode connected to the second output electrode of one of said pair of transistors; said third transistor having its second output electrode connected to a negative voltage line; each of said read word lines being connected to one of said rows of said memory cells functioning as said storage cells through any of said storage word lines connected to the row to produce an output when the row of said memory cells functioning as said storage cells satisfies the search argument so that the potential on any of said stroage word lines connected to said read word line is not reduced; and said third transistor of said read cell being conductive when the potential of said connected read word line is not reduced to produCe a potential on said read line, the magnitude of the potential produced on said read line being higher when one of said transistors of said pair of transistors of said read cell is saturated than when the other of said transistors of said pair of transistors of said read cell is saturated so as to indicate the state of said read cell in accordance with which of said pair of transistors is saturated.

Claim 16

The array according to claim 13 in which each of said word lines connected to said memory cells functioning as said storage cells is connected with said memory cells in both the odd and even columns of said memory cells in one of the rows of said memory cells.

Claim 17

The array according to claim 13 in which each of said word lines connected to said memory cells functioning as said storage cells is connected only with said memory cells in the odd or even columns of one of the rows of said memory cells.

Claim 18

The array according to claim 12 in which: said separate means includes memory cells arranged in rows and columns, a read cell being formed by each of said memory cells; each of said separate means comprises the odd or even columns of said read cells in one of said rows; each of said read cells includes: a pair of transistors; each of said transistors having a first output electrode, a second output electrode, and a control electrode; means cross coupling the first output electrode of each of said transistors to the control electrode of the other of said transistors whereby said pair of transistors forms a bistable circuit; a separate constant current source connected to the first output electrode of each of said pair of transistors, and a third transistor having a first output electrode, a second output electrode, and a control electrode; a plurality of read word lines; each of said read word lines being connected with said read cells in only the odd or even columns of one of the rows of said read cells; each of said transistors of said pair of transistors of said read cells having the second output electrode connected to one of said read word lines; a plurality of read lines with each associated with two adjacent columns of said read cells; each of said read lines being connected to the first output electrode of each of said third transistors of said read cells in the two adjacent columns; said third transistor having its control electrode connected to the second output electrode of one of said pair of transistors; said third transistor having its second output electrode connected to a negative voltage line; each of said read word lines being connected to one of said rows of said memory cells functioning as said storage cells through any of said connected storage word lines to produce an output when the row of said memory cells functioning as said storage cells satisfies the search argument so that the potential on any of said storage word lines connected to said read word line is not reduced; and said third transistor of said read cell being conductive when the potential of said connected read word line is not reduced to produce a potential on said read line, the magnitude of the potential produced on said read line being higher when one of said transistors of said pair of transistors of said read cell is saturated than when the other of said transistors of said pair of transistors of said read cell is saturated so as to indicate the state of said read cell in accordance with which of said pair of transistors is saturated.

Claim 19

The array according to claim 16 in which each of said word lines connected to said memory cells functioning as said storage cells is connected with said memory cells in both the odd and even columns of said memory cells in one of the rows of said memory cells.

Claim 20

The array according to claim 16 in which each of said word lines connected to said memory cells functioning as said storage cells is connected only with said memory cells in the odd or Even columns of one of the rows of said memory cells.

Claim 21

The array according to claim 12 in which each of said word lines is connected with said memory cells in both the odd and even columns of said memory cells in one of the rows of said memory cells.

Claim 22

The array according to claim 12 in which each of said word lines is connected only with said memory cells in the odd or even columns of one of the rows of said memory cells.

Claim 23

An associative array having: memory cells arranged in rows and columns, a read cell being formed by each of said memory cells; each of said read cells including: a pair of transistors; each of said transistors having a first output electrode, a second output electrode, and a control electrode; means cross coupling the first output electrode of each of said transistors to the control electrode of the other of said transistors whereby said pair of transistors forms a bistable circuit; a separate constant current source connected to the first output electrode of each of said pair of transistors; and a third transistor having a first output electrode, a second output electrode, and a control electrode; a plurality of word lines; each of said word lines being connected with said read cells in only the odd or even columns of one of the rows of said read cells; each of said transistors of said pair of transistors having the second output electrode connected to one of said word lines; a plurality of read lines with each associated with two adjacent columns of said read cells; each of said read lines being connected to the first output electrode of each of said third transistors of said read cells in the two adjacent columns; said third transistor having its control electrode connected to the second output electrode of one of said pair of transistors; said third transistor having its second output electrode connected to a negative voltage line; each of said word lines being connected to a source of potential that decreases when said connected read cells are not to produce an output on said read lines; and said third transistor being conductive when the potential of said word line is not reduced to produce a potential on said read line, the magnitude of the potential produced on said read line being higher when one of said transistors of said pair of transistors is saturated than when the other of said transistors of said pair of transistors is saturated so as to indicate the state of said read cell in accordance with which of said pair of transistors is saturated.

Claim 24

An associative array having: memory cells arranged in rows and columns, a read cell being formed by each of said memory cells; each of said read cells including: a pair of transistors; each of said transistors having a first output electrode, a second output electrode, and a control electrode; means cross coupling the first output electrode of each of said transistors to the control electrode of the other of said transistors whereby said pair of transistors forms a bistable circuit; a separate constant current source connected to the first output electrode of each of said pair of transistors; and a third transistor having a first output electrode, a second output electrode, and a control electrode; a plurality of word lines; each of said word lines being connected with said read cells in only the odd or even columns of one of the rows of said read cells; each of said transistors of said pair of transistors having the second output electrode connected to one of said word lines; a plurality of read lines with each associated with two adjacent columns of said read cells; each of said read lines being connected to the first output electrode of each of said third transistors of said read cells in the two adjacent columns; said third transistor having its control electrode connected to the second output electrode of one of said pair of transistors; said third transistor having its second output electrode connected to a negative voltage line; each of said word lines being connected to a source of potential that decreases when said connected read cells are not to produce an output on said read lines; and said third transistor being conductive when the potential of said word line is not reduced to produce a potential on said read line, the magnitude of the potential produced on said read line being higher when one of said transistors of said pair of transistors is saturated than when the other of said transistors of said pair of transistors is saturated so as to indicate the state of said read cell in accordance with which of said pair of transistors is saturated.