Memory access circuit with pointer shifting network

Claim 2

A memory apparatus including memory cells for storing data entries in adjacent ones of said memory cells comprising: an occupancy bit associated with each of said cells for developing a memory cell pointer based on the occupancy pattern of said memory cells to identify an end occupied cell having an unoccupied cell adjacent thereto; a pointer shifting network for displacing said pointer by a number, in the range 1 to N, where N is greater than 1, in response to an applied displacement value, for pointing to an occupied cell that is removed from said end occupied cell by said applied value; and means for accessing said occupied cell.

Claim 3

The memory apparatus of claim 1 wherein said memory cells include means for simultaneously shifting data entries on one side of said displaced pointer to adjacent memory cells.

Claim 4

A memory apparatus in accordance with claim 1 wherein said pointer is multidigit word and said means for displacing said pointer is a plus-minus 2i shift network executing a shift in accordance with said applied displacement value.

Claim 5

A memory apparatus comprising a memory means for storing a data list in a contiguous set of memory cells, forming a block having a cell at each of two ends; and memory access means responsive to an applied displacement address signal of a selected alterable integer value including (a) first means for generating a reference pointer signal pointing to one of said ends, (b) second means for altering said pointer in accordance with said applied displacement address signal, and for thereby pointing to a cell within said block that is removed from the end pointed to by said first means by said applied displacement address signal, and third means for accessing a cell in said memory displaced from said reference pointer by a number of cells as determined by said displacement address signal.

Claim 6

A memory apparatus comprising a memory means for storing a data list in a contiguous set of memory cells, forming a block having a cell at each of two ends; and memory access means responsive to an applied displacement address signal of a selected alterable integer value including (a) first means for generating a reference pointer signal pointing to one of said ends, (b) second means for altering said pointer in accordance with said applied displacement address signal, and for thereby pointing to a cell within said block that is removed from the end pointed to by said first means by said applied displacement address signal, and third means for accessing a cell in said memory displaced from said reference pointer by a number of cells as determined by said displacement address signal.

Claim 7

The memory apparatus of claim 4 wherein said memory access means further includes means responsive to a mode signal indicating different modes of operation, for performing the operation specified by said mode signal at said data entry location accessed by said memory access means.

Claim 8

The memory apparatus of claim 4 wherein said memory access means further includes means for generating a carry signal when the displacement introduced by said displacement address exceeds the number of locations between said reference pointer and the end of said memory in the direction of said displacement.

Claim 9

A memory system including a plurality of memory elements for storing information applied to a signal bus of said memory system in an ordered fashion within said memory elements to form a list of stored information that preserves the order in which said information is stored and permits the reading of said stored information by applying said stored information to said signal bus, said writing and reading occurring in accordance with individualized control signals applied to each of said memory elements comprising: an occupancy bit associated with each of said memory elements for indicating whether the associated memory element is occupied with stored information; a plurality of control elements, each associated with one of said memory elements and occupancy bits, responsive to its associated occupancy bit, to two other occupancy bits and to a mode control signal specifying a sought characteristic, for developing an output signal indicative of whether the associated memory element possesses said sought characteristic, with the collection of said output signals comprising a pointer signal; and a pointer shifting network, responsive to a displacement address and to said pointer signal, for developing a shifted pointer signal applied to said plurality of control elements to develop said individualized control signals.

Claim 10

A memory system including a plurality of memory elements for storing information applied to a signal bus of said memory system in an ordered fashion within said memory elements to form a list of stored information that preserves the order in which said information is stored and permits the reading of said stored information by applying said stored information to said signal bus, said writing and reading occurring in accordance with individualized control signals applied to each of said memory elements comprising: an occupancy bit associated with each of said memory elements for indicating whether the associated memory element is occupied with stored information; a plurality of control elements, each associated with one of said memory elements and occupancy bits, responsive to its associated occupancy bit, to two other occupancy bits and to a mode control signal specifying a sought characteristic, for developing an output signal indicative of whether the associated memory element possesses said sought characteristic, with the collection of said output signals comprising a pointer signal; and a pointer shifting network, responsive to a displacement address and to said pointer signal, for developing a shifted pointer signal applied to said plurality of control elements to develop said individualized control signals.

Claim 11

A memory system comprising: a plurality of information storing memory modules, each responsive to a mode control signal, to a first portion of a displacement address and to an enable signal and developing a pointer signal indicative of the existence in said module of a stored information condition defined by said mode signal; and switching means responsive to said pointer signals and to a second portion of said displacement address for developing said enable signal for each of said memory modules each of said memory modules further comprises means for developing an occupancy signal indicative of whether said memory module is at a condition of being empty, fully populated with stored information, or partially populated with stored information; means for developing a shadow signal that mimics the occupancy signal of that one of said memory modules whose occupancy signal indicates that the memory module is at a condition of being partially populated with stored information; control means responsive to said occupancy signal for developing said pointer signal; and shift means responsive to said second portion of the displacement address for shifting said shadow signal and applying its shifted output signal to said control means.

Claim 12

A memory system comprising: a plurality of information storing memory modules, each responsive to a mode control signal, to a first portion of a displacement address and to an enable signal and developing a pointer signal indicative of the existence in said module of a stored information condition defined by said mode signal; and switching means responsive to said pointer signals and to a second portion of said displacement address for developing said enable signal for each of said memory modules each of said memory modules further comprises means for developing an occupancy signal indicative of whether said memory module is at a condition of being empty, fully populated with stored information, or partially populated with stored information; means for developing a shadow signal that mimics the occupancy signal of that one of said memory modules whose occupancy signal indicates that the memory module is at a condition of being partially populated with stored information; control means responsive to said occupancy signal for developing said pointer signal; and shift means responsive to said second portion of the displacement address for shifting said shadow signal and applying its shifted output signal to said control means.