Single mask totally self-aligned power MOSFET cell fabrication process

Claim 1

A process for making a multicell power MOSFET comprising the steps of preparing a monocrystalline silicon wafer whose bulk is of one conductivity type, forming in turn over one surface of the wafer a thermally-grown oxide layer and a polysilicon layer, oxidizing the top surface portion of the polysilicon layer to form of it a polyoxide layer, forming openings at least through the polyoxide and polysilicon layers for defining localized portions of the wafer, introducing donor and acceptor ions into the silicon wafer by way of said openings for forming an enclosed surface zone of the one conductivity type, adjacent each of said openings and a separate zone of the opposite conductivity enclosing each of said surface zones, each of the enclosing zones including a surface region essentially all of which underlies the polysilicon layer so that, when inverted, it can serve as a conductive channel between the enclosed surface zone of the one conductivity type and the bulk of the wafer of the one conductivity type, forming an insulating layer over the edges of the polysilicon layer exposed in each opening, depositing a conductive layer over the polyoxide layer and in the openings for penetrating the thermally-grown oxide layer in the openings and making low resistance electrical connection at least to each of the surface regions of the one conductivity type, and providing a separate low resistance electrical connection to the bulk of the wafer.