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US4885257A Expired / Lapsed US ⏱️ 0.0 years remaining

Gettering process with multi-step annealing and inert ion implantation

Assignee: Toshiba Corp
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Filing: 1987-06-02
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Granted: 1989-12-05
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Expires: 2007-06-02
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Abstract

Abstract A semiconductor substrate and process for making are disclosed. The substrate is suitable for use in manufacturing large scale integrated circuits. The process comprises the steps of heating a semiconductor substrate at a temperature not lower than 1100° C., implanting electrically inert impurities into the major surface of the substrate, heating the substrate at a temperature ranging from 600° to 900° C. and providing a single crystal semiconductor layer.

Inventors

  • 👤 Yoshiaki Matsushita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 10:47
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P36/00; H10P36/03; Y; Y10; Y10S; Y10S148/00; Y10S148/003; Y10S148/024; Y10S148/06; Y10S148/076; Y10S148/083; Y10S148/097; Y10S148/127

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 165 words
A process for producing a semiconductor substrate comprising the steps of: heating a semiconductor substrate material with a first resistivity at a temperature not less than 1100° C. in order to change a major surface of said substrate material into a high resistivity semiconductor layer with a second resistivity higher than said first resistivity, said high resistivity semiconductor layer having resistivity more than 1 ohm cm at a depth of 1.5 um from said major surface of said substrate material, implanting electrically inert impurities into said major surface of said substrate material to produce defect centers in said high resistivity semiconductor layer. heating said substrate material at a temperature ranging from 600° to 900° C. to generate micro defects in both of said substrate material and said high resistivity semiconductor layer, and providing a single crystal semiconductor layer with a third resistivity between said first and second resistivity on said major surface of said substrate material, said third resistivity being larger than said first resistivity.
Claim 2
Dependent Claim 165 words
A process for producing a semiconductor substrate comprising the steps of: heating a semiconductor substrate material with a first resistivity at a temperature not less than 1100° C. in order to change a major surface of said substrate material into a high resistivity semiconductor layer with a second resistivity higher than said first resistivity, said high resistivity semiconductor layer having resistivity more than 1 ohm cm at a depth of 1.5 um from said major surface of said substrate material, implanting electrically inert impurities into said major surface of said substrate material to produce defect centers in said high resistivity semiconductor layer. heating said substrate material at a temperature ranging from 600° to 900° C. to generate micro defects in both of said substrate material and said high resistivity semiconductor layer, and providing a single crystal semiconductor layer with a third resistivity between said first and second resistivity on said major surface of said substrate material, said third resistivity being larger than said first resistivity.
Claim 3
Dependent Claim 52 words
A process for producing a semiconductor substrate according to claim 1 wherein said substrate material contains a dopant element in an amount of not lower than 1×10 16 /cm 3 and said single crystal semiconductor layer contains a dopant element in an amount of not higher than 5×10 15 /cm 3 .
Claim 4
Dependent Claim 51 words
A process for producing the semiconductor substrate according to claim 1 wherein said impurities implanted into said major surface are at least one member selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), silicon (Si), germanium (Ge), tin (Sn), argon (Ar), xenon (Xe), krypton (Kr) and neon (Ne).

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-12-04 1993-06-05 1993-12-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-12-04 1997-06-05 1997-12-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-12-04 2001-06-05 2001-12-05 $7700.00 Window Closed / Lapsed

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