US4608096A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gettering
Assignee: SunEdison Inc
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Filing: 1985-06-28
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Granted: 1986-08-26
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Expires: 2005-06-28
Abstract
Abstract Semiconductor substrate materials, such as silicon, useful in the manufacture of electronic devices, such as integrated circuits, employing low temperature, i.e., below 1025° C. processing cycles are provided with a 0.05 to 2.0 micron thick layer of polysilicon on the backside to improve gettering capabilities of defects, contaminants and impurities away from the active device region of the substrate.
Inventors
- 👤 Dale E. Hill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:30
CPC Classifications
H; H10; H10P; H10P36/00; H10P36/20; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3438; H10P14/3441; H10P14/60; H10P36/03; Y; Y10; Y10S; Y10S148/00; Y10S148/06
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
66 words
A semiconductor substrate with capability for gettering defects, contaminants and impurities deleterious to electronic devices to a region away from the active device region consisting essentially of a semiconductor material having a 0.05 to 5.0 microns thick layer on the backside of the substrate from the device region of polysilicon containing a dopant element in an amount of 0.1 to 40 weight percent of said layer.
Claim 2
Dependent Claim
66 words
A semiconductor substrate with capability for gettering defects, contaminants and impurities deleterious to electronic devices to a region away from the active device region consisting essentially of a semiconductor material having a 0.05 to 5.0 microns thick layer on the backside of the substrate from the device region of polysilicon containing a dopant element in an amount of 0.1 to 40 weight percent of said layer.
Claim 3
Dependent Claim
19 words
The substrate of claim 1 wherein the thickness of said doped polysilicon layer is from 0.2 to 2.0 microns.
Claim 4
Dependent Claim
19 words
The substrate of claim 1 wherein the thickness of said doped polysilicon layer is from 0.6 to 1.0 micron.
Claim 5
Dependent Claim
10 words
The substrate of claim 1 wherein said dopant is oxygen.
Claim 6
Dependent Claim
10 words
The substrate of claim 1 wherein said dopant is nitrogen.
Claim 7
Dependent Claim
28 words
The substrate of claim 1 wherein the dopant element is present in said layer in an amount of from about 2 to 20 weight percent of said layer.
Claim 8
Dependent Claim
27 words
The substrate of claim 1 wherein the dopant element is present in said layer in an amount from about 4 to 10 weight percent of said layer.
Claim 9
Dependent Claim
10 words
The substrate of claim 1 wherein semiconductor material is silicon.
Claim 10
Dependent Claim
32 words
The substrate of claim 1 wherein said doped polysilicon layer is applied to said semiconductor material by chemical vapor deposition of a silicon containing material in the presence of a dopant material.
Claim 11
Dependent Claim
11 words
The substrate of claim 9 wherein said silicon-containing material is silane.
Claim 12
Dependent Claim
18 words
The substrate of claim 9 wherein said silicon-containing material is silane and said dopant material is nitrogen oxide.
Claim 13
Dependent Claim
56 words
A semiconductor substrate with capability for gettering defects, contaminants and impurities deleterious to electronic devices to a region away from the active device region consisting essentially of a silicon wafer having one mirror-like surface and a 0.2 to 2.0 microns thick layer of oxygen-doped polysilicon containing 0.1 to 40 weight percent oxygen covering the other surface.
Claim 14
Dependent Claim
56 words
A semiconductor substrate with capability for gettering defects, contaminants and impurities deleterious to electronic devices to a region away from the active device region consisting essentially of a silicon wafer having one mirror-like surface and a 0.2 to 2.0 microns thick layer of oxygen-doped polysilicon containing 0.1 to 40 weight percent oxygen covering the other surface.
Claim 15
Dependent Claim
15 words
The substrate of claim 12 wherein said layer is from 0.6 to 1.0 micron thick.
Claim 16
Dependent Claim
23 words
The substrate of claim 12 wherein oxygen is present in said layer from about 2.0 to about 20 weight percent of said layer.
Claim 17
Dependent Claim
23 words
The substrate of claim 12 wherein oxygen is present in said layer from about 4.0 to about 10 weight percent of said layer.
Claim 18
Dependent Claim
49 words
A process for manufacturing electronic devices using thermal processing conditions wherein the devices are formed on one surface of a substrate consisting essentially of a semiconductor material having a backside layer of polysilicon containing a dopant element in an amount of 0.1 to 40 weight percent of the layer.
Claim 19
Dependent Claim
49 words
A process for manufacturing electronic devices using thermal processing conditions wherein the devices are formed on one surface of a substrate consisting essentially of a semiconductor material having a backside layer of polysilicon containing a dopant element in an amount of 0.1 to 40 weight percent of the layer.
Claim 20
Dependent Claim
18 words
The process of claim 16 wherein the doped polysilicon layer has a thickness from 0.05 to 5.0 microns.
Claim 21
Dependent Claim
14 words
The process of claim 17 wherein said thickness is from 0.2 to 2.0 microns.
Claim 22
Dependent Claim
14 words
The process of claim 17 wherein said thickness is from 0.6 to 1.0 micron.
Claim 23
Dependent Claim
11 words
The process of claim 16 wherein said semiconductor material is silicon.
Claim 24
Dependent Claim
24 words
The process of claim 16 wherein said dopant element is oxygen present in said layer in an amount from 2.0 to 20 weight percent.
Claim 25
Dependent Claim
24 words
The process of claim 16 wherein said dopant element is oxygen present in said layer in an amount from 4.0 to 10 weight percent.
Claim 26
Dependent Claim
59 words
A process of manufacturing electronic devices wherein the devices are formed under thermal conditions on and near one surface of a silicon wafer having a layer consisting essentially of oxygen-doped polysilicon on the other surface, the layer of oxygen-doped polysilicon having a thickness from 0.2 to 2.0 microns and an oxygen content of from 0.1 to 40 weight percent.
Claim 27
Dependent Claim
59 words
A process of manufacturing electronic devices wherein the devices are formed under thermal conditions on and near one surface of a silicon wafer having a layer consisting essentially of oxygen-doped polysilicon on the other surface, the layer of oxygen-doped polysilicon having a thickness from 0.2 to 2.0 microns and an oxygen content of from 0.1 to 40 weight percent.
Claim 28
Dependent Claim
14 words
The process of claim 23 wherein said thickness is from 0.6 to 1.0 micron.
Claim 29
Dependent Claim
22 words
The process of claim 23 wherein said oxygen is present in said layer in an amount from 2.0 to 20 weight percent.
References Cited (Backward Citations)
US4053335A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-25 | 1990-02-24 | 1990-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-25 | 1994-02-24 | 1994-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-25 | 1998-02-24 | 1998-08-26 | $7700.00 | Window Closed / Lapsed |