US4884238A — Read-only memory

Claim 1

Independent Claim 425 words

A monolithic integrated memory circuit, said memory comprising: a semiconductor material body of a first conductivity type in at least a first portion thereof, forming a first body portion, except in a plurality of isolating regions in said first body portion which plurality includes multiple pluralities of said isolating regions each of which has those said isolating regions included therein electrically interconnected to one another to form an interconnection plurality thereby forming multiple interconnection pluralities of said isolating regions, said semiconductor material body having a first major surface which is intersected by selected ones of said plurality of isolating regions with each of said isolating regions being of a second conductivity type; a plurality of memory point regions which comprises multiple first constituent pluralities of said memory point regions with each of said multiple interconnection pluralities of said isolating regions having those said memory point regions of one of said first constituent pluralities located therein, said plurality of memory point regions also comprising multiple second constituent pluralities of said memory point regions with each of said second constituent pluralities having one of those said memory point regions therein located in each one of said multiple interconnection pluralities of said isolating regions, each said memory point regions being of said first conductivity type and intersecting said first major surface but otherwise being surrounded by that said selected isolating region in which that said memory point region is located; a plurality of first interconnection means with there being one of said first interconnection means electrically connected to each of said multiple interconnection pluralities of said isolating regions, and to a first circuit selection means; a plurality of second interconnection means each being electrically connected to a terminating region of a field-effect transistor in a second circuit selection means, there being one of said plurality of second interconnection means being provided for each of said second constituent pluralities but with only selected ones of those said memory point regions in a said second constituent plurality thereof being electrically connected to that said second interconnection means corresponding thereto; and a plurality of second interconnection means impedances each having first and second terminating regions between which a selected conductivity is established, said first terminating region of each of said plurality of second interconnection means impedances being electrically connected to a first terminal means adapted for connection to a first source of voltage, said second terminating region of each of said plurality of second interconnection means impedances being electrically connected to a corresponding one of said plurality of second interconnection means.

Claim 2

Dependent Claim 425 words

A monolithic integrated memory circuit, said memory comprising: a semiconductor material body of a first conductivity type in at least a first portion thereof, forming a first body portion, except in a plurality of isolating regions in said first body portion which plurality includes multiple pluralities of said isolating regions each of which has those said isolating regions included therein electrically interconnected to one another to form an interconnection plurality thereby forming multiple interconnection pluralities of said isolating regions, said semiconductor material body having a first major surface which is intersected by selected ones of said plurality of isolating regions with each of said isolating regions being of a second conductivity type; a plurality of memory point regions which comprises multiple first constituent pluralities of said memory point regions with each of said multiple interconnection pluralities of said isolating regions having those said memory point regions of one of said first constituent pluralities located therein, said plurality of memory point regions also comprising multiple second constituent pluralities of said memory point regions with each of said second constituent pluralities having one of those said memory point regions therein located in each one of said multiple interconnection pluralities of said isolating regions, each said memory point regions being of said first conductivity type and intersecting said first major surface but otherwise being surrounded by that said selected isolating region in which that said memory point region is located; a plurality of first interconnection means with there being one of said first interconnection means electrically connected to each of said multiple interconnection pluralities of said isolating regions, and to a first circuit selection means; a plurality of second interconnection means each being electrically connected to a terminating region of a field-effect transistor in a second circuit selection means, there being one of said plurality of second interconnection means being provided for each of said second constituent pluralities but with only selected ones of those said memory point regions in a said second constituent plurality thereof being electrically connected to that said second interconnection means corresponding thereto; and a plurality of second interconnection means impedances each having first and second terminating regions between which a selected conductivity is established, said first terminating region of each of said plurality of second interconnection means impedances being electrically connected to a first terminal means adapted for connection to a first source of voltage, said second terminating region of each of said plurality of second interconnection means impedances being electrically connected to a corresponding one of said plurality of second interconnection means.

Claim 3

Dependent Claim 49 words

The memory of claim 1 wherein there is one said memory point region from a said corresponding first constituent of memory point regions in each said electrically interconnected selected isolating region in that one of said multiple interconnection pluralities of isolating regions corresponding to that said first constituent plurality.

Claim 4

Dependent Claim 54 words

The memory of claim 1 wherein there is more than one said memory point region from a said first constituent plurality of memory point regions in at least one of said electrically interconnected selected isolating regions in that one of said multiple interconnection pluralities of isolating regions corresponding to that said first constituent plurality.

Claim 5

Dependent Claim 43 words

The memory wherein each said electrically interconnected selected isolating region in one of said multiple interconnection pluralities of isolating regions is electrically interconnected by a portion of said semiconductor material body of said second conductivity type to thereby form a continuous isolating region.

Claim 6

Dependent Claim 43 words

The memory wherein each said electrically interconnected selected isolating region in one of said multiple interconnection pluralities of isolating regions is electrically interconnected by a portion of said semiconductor material body of said second conductivity type to thereby form a continuous isolating region.

Claim 7

Dependent Claim 61 words

The memory of claim 1 wherein each memory point region is separated by that said selected isolating region in which it is located from remaining parts of said first body portion of said first conductivity type, excluding other said memory point regions, by a distance sufficiently small to permit bipolar transistor action with that selected isolating region serving as a base.

Claim 8

Dependent Claim 91 words

The memory of claim 1 wherein each of said plurality of second interconnection impedance means is a transistor means having its first and second terminating regions serving as said terminating regions of said second interconnection impedance means and located in a said selected isolating region as a second interconnection transistor means, each said second interconnection transistor means having a control region therein by which it is capable of being directed, through electrical energization thereof, to effectively provide a conductive path between its first and second terminating regions of a selected conductivity.

Claim 9

Dependent Claim 34 words

The memory of claim 6 wherein each of said second interconnection transistor means in said plurality thereof is a field-effect transistor means each having drain and source regions serving as its said terminating regions.

Claim 10

Dependent Claim 75 words

The memory of claim 6 wherein there is further provided a plurality of second interconnection control transistors in said second circuit selection means each being a field-effect transistor and having first and second terminating regions therein located in a said selected isolating region and having a gate region therein, each of said second interconnection means being electrically connected to a corresponding one of said second interconnection means control transistor means at its first terminating region.

Claim 11

Dependent Claim 61 words

The memory of claim 8 wherein each memory point region is separated by that said selected isolating region in which it is located from remaining parts of said first body portion of said first conductivity type, excluding other said memory point regions, by a distance sufficiently small to permit bipolar transistor action with that selected isolating region serving as a base.

Claim 12

Dependent Claim 93 words

The memory of claim 8 wherein a sensing means is electrically connected to said second interconnection control transistor means second terminating region, said sensing means having transistor means therein each having first and second terminating regions therein and having a control region therein by which it is capable of being directed, through electrical energization thereof, to effectively provide a conductive path between its first and second terminating regions of a selected conductivity, said second interconnection control transistor means second terminating region being electrically connected solely to said sensing means transistor means control regions.

Claim 13

Dependent Claim 61 words

The memory of claim 10 wherein each memory point region is separated by that said selected isolating region in which it is located from remaining parts of said first body portion of said first conductivity type, excluding other said memory point regions, by a distance sufficiently small to permit bipolar transistor action with that selected isolating region serving as a base.

Claim 14

Dependent Claim 59 words

The memory of claim 10 wherein each of said second interconnection transistor means in said plurality thereof in a field-effect transistor means each having drain and source regions serving as its said terminating regions, and each of said sensing means transistor means is a field-effect transistor means each having drain and source regions serving as its said terminating regions.

Claim 15

Dependent Claim 109 words

The memory of claim 8 wherein said second interconnection control transistor means second terminating region is electrically connected to a sensing means, said sensing means having therein transistor means having first and second terminating regions located in a said first body portion outside of said selected isolating regions and having a control region therein by which it is capable of being directed, through electrical energization thereof, to effectively provide a conductive path between its first and second terminating regions of a selected conductivity, said second interconnection control transistor means second terminating region being electrically connected to said sensing means transistor means terminating regions solely through a fixed impedance means.

Claim 16

Dependent Claim 59 words

The memory of claim 13 wherein each of said second interconnection transistor means in said plurality thereof is a field-effect transistor means each having drain and source regions serving as its said terminating regions, and each of said sensing means transistor means is a field-effect transistor means each having drain and source regions serving as its said terminating regions.

Claim 17

Dependent Claim 105 words

The memory of claim 8 wherein said second interconnection control transistor means second terminating region is electrically connected to a sensing means, said sensing means having first and second inverters therein each having an input and an output such that an opposite logic level occurs at an output from that logic level applied to an input, said second interconnection control transistor means second terminating region being electrically connected to said input of said first inverter, said first inverter output being electrically connected to said second inverter input, and said second inverter output being electrically connected through a fixed impedance means to said first inverter input.

Claim 18

Dependent Claim 59 words

The memory of claim 15 wherein each of said second interconnection transistor means in said plurality thereof is a field-effect transistor means each having drain and source regions serving as its said terminating regions, and each of said sensing means transistor means is a field-effect transistor means each having drain and source regions serving as its said terminating regions.

Claim 19

Dependent Claim 17 words

The memory of claim 8 wherein each second interconnection control transistor is a metal-oxide-semiconductor field-effector transistor (MOSFET).

Claim 20

Dependent Claim 61 words

The apparatus of claim 6 wherein each memory point region is separated by that said selected isolating region in which it is located from remaining parts of said first body portion of said first conductivity type, excluding other said memory point regions, by a distance sufficiently small to permit bipolar transistor action with that selected isolating region serving as a base.

Claim 21

Dependent Claim 102 words

The memory of claim 1 wherein there is further provided a plurality of first interconnection first control transistor means in said first circuit selection means each having first and second terminating regions therein located in a said selected isolating region and having a control region therein by which it is capable of being directed, through electrical energization thereof, to effectively provide a conductive path between its first and second terminating regions of a selected conductivity with each of said first interconnection means being electrically connected to a corresponding one of said first interconnection first control transistor means at its second terminating region.

Claim 22

Dependent Claim 101 words

The memory of claim 19 wherein there is further provided a plurality of first interconnection second control transistor means in said first circuit selection means each having first and second terminating regions therein located in said first body portion and having a control region therein by which it is capable of being directed, through electrical energization thereof, to effectively provide a conductive path between its first and second terminating regions of a selected conductivity with each of said first interconnection means being electrically connected to a corresponding one of said first interconnection second control transistor means at its first terminating region.

Claim 23

Dependent Claim 251 words

A memory circuit, said circuit comprising an array of diodes each having a pair of terminating regions serving as anodes and cathodes thereof, said array of diodes comprising first multiple pluralities of initial terminating region-connected diodes such that an initial one of said pair of terminating regions of those said diodes in any one of said first multiple pluralities are electrically interconnected to one another, and each remaining one of said pair of terminating regions in a said diode, in any one of those said first multiple pluralities, corresponding to one remaining terminating region in a said diode in each of those other ones of said first multiple pluralities to thereby form second multiple pluralities of corresponding diodes; a first circuit selection means electrically connected to said initial terminating regions in each one of said first multiple pluralities; a plurality of field-effect transistors each having a pair of terminating regions serving as source and drain thereof and a gate region with there being one said field-effect transistor corresponding to each one of said second multiple pluralities, and with selected ones of said remaining terminating regions of those said diodes in each one of second multiple pluralities being electrically connected to one of said pair of terminating regions of its corresponding said field-effect transistor; and a second circuit selection means electrically connected to each of those said terminating regions of said plurality of field-effect transistors that are electrically connected to diodes in a corresponding one of said second multiple pluralities as aforesaid.

Claim 24

Dependent Claim 251 words

A memory circuit, said circuit comprising an array of diodes each having a pair of terminating regions serving as anodes and cathodes thereof, said array of diodes comprising first multiple pluralities of initial terminating region-connected diodes such that an initial one of said pair of terminating regions of those said diodes in any one of said first multiple pluralities are electrically interconnected to one another, and each remaining one of said pair of terminating regions in a said diode, in any one of those said first multiple pluralities, corresponding to one remaining terminating region in a said diode in each of those other ones of said first multiple pluralities to thereby form second multiple pluralities of corresponding diodes; a first circuit selection means electrically connected to said initial terminating regions in each one of said first multiple pluralities; a plurality of field-effect transistors each having a pair of terminating regions serving as source and drain thereof and a gate region with there being one said field-effect transistor corresponding to each one of said second multiple pluralities, and with selected ones of said remaining terminating regions of those said diodes in each one of second multiple pluralities being electrically connected to one of said pair of terminating regions of its corresponding said field-effect transistor; and a second circuit selection means electrically connected to each of those said terminating regions of said plurality of field-effect transistors that are electrically connected to diodes in a corresponding one of said second multiple pluralities as aforesaid.

Claim 25

Dependent Claim 47 words

The circuit of claim 21 wherein said initial terminating regions of those said diodes in any one of said first multiple pluralities electrically connected to one another are cathodes of said diodes, and each said remaining terminating region in such a said diode is an anode thereof.

Claim 26

Dependent Claim 18 words

The circuit of claim 21 wherein said plurality of field-effect transistors are each a metal-oxide-semiconductor field-effect transistor (MOSFET).

Claim 27

Dependent Claim 244 words

A memory circuit, said circuit comprising: an array of bipolar transistors having collectors thereof electrically interconnected to one another, said array of bipolar transistors comprising first multiple pluralities of base-interconnected bipolar transistors such that bases of those said transistors in any one of those said first multiple pluralities thereof are electrically interconnected to one another, and each bipolar transistor having an emitter such that each emitter in a said bipolar transistor, in any one of those said first multiple pluralities, corresponds to one emitter in a said bipolar transistor in each of those other ones of said first multiple pluralities remaining to thereby form second multiple pluralities of corresponding bipolar transistors; a first circuit selection means electrically connected to said bases in each one of said first multiple pluralities; a plurality of field-effect transistors each having a pair of terminating regions serving as sources and drains thereof and a gate region with there being one of said field-effect transistors corresponding to each one of said second multiple pluralities, and with selected ones of said emitters of those said bipolar transistors in each one of said second multiple pluralities being electrically connected to one of said pair of terminating regions of its corresponding said field-effect transistor; and a second circuit selection means electrically connected to each of those said terminating regions of each of said field-effect transistors that are electrically connected to bipolar transistors in a corresponding one of said second multiple pluralities as aforesaid.

Claim 28

Dependent Claim 244 words

A memory circuit, said circuit comprising: an array of bipolar transistors having collectors thereof electrically interconnected to one another, said array of bipolar transistors comprising first multiple pluralities of base-interconnected bipolar transistors such that bases of those said transistors in any one of those said first multiple pluralities thereof are electrically interconnected to one another, and each bipolar transistor having an emitter such that each emitter in a said bipolar transistor, in any one of those said first multiple pluralities, corresponds to one emitter in a said bipolar transistor in each of those other ones of said first multiple pluralities remaining to thereby form second multiple pluralities of corresponding bipolar transistors; a first circuit selection means electrically connected to said bases in each one of said first multiple pluralities; a plurality of field-effect transistors each having a pair of terminating regions serving as sources and drains thereof and a gate region with there being one of said field-effect transistors corresponding to each one of said second multiple pluralities, and with selected ones of said emitters of those said bipolar transistors in each one of said second multiple pluralities being electrically connected to one of said pair of terminating regions of its corresponding said field-effect transistor; and a second circuit selection means electrically connected to each of those said terminating regions of each of said field-effect transistors that are electrically connected to bipolar transistors in a corresponding one of said second multiple pluralities as aforesaid.

Claim 29

Dependent Claim 18 words

The circuit of claim 24 wherein said plurality of field-effect transistors are each a metal-oxide-semiconductor field-effect transistor (MOSFET).

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1992-11-27	1993-05-29	1993-11-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1996-11-27	1997-05-29	1997-11-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2000-11-27	2001-05-29	2001-11-28	$7700.00	Window Closed / Lapsed

Read-only memory

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