Scan data path coupling

Claim 1

In a digital logic unit of the type including a plurality of logic elements, such as AND gates and OR gates, and elemental memory units (MUs), such a flip-flops, latches, registers, and counters, that are connected to function as a part of the logic unit during a normal mode, where the MUs are serially connected to form the register elements of a scan line shift register (SR) during a scan mode, where a system clock signal (SCLK) is received at an SCLK input, and where the scan SR is used to shift a scan data pattern, received at a scan SR input, into the SR register elements during the scan mode to test the operability of the stages and interconnections of the logic unit, a system for preventing corruption of the scan data pattern comprising: means, coupled to every SR register element, for serially connecting the SR register elements during the scan mode with each SR register element having a clock input for receiving a delayed version of SCLK with the magnitude of the delay relative to the undelayed SCLK signal determined by the delays induced by the particular logic elements connecting the SCLK input port to said clock input of a particular SR register element; a first scan sub-chain of serially connected SR register elements including only SR register elements receiving a delayed version of SCLK having a delay of a first fixed magnitude; a second scan sub-chain of serially connected SR register elements including only SR register elements receiving a delayed version of SCLK having a delay of a second fixed magnitude, with said first magnitude being greater than said second magnitude and with said first scan sub-chain being nearer to the scan SR input than said second scan sub-chain.