Test/master/slave triple latch flip-flop

Claim 2

A shift register stage for large-scale integrated and very large-scale integrated circuits, comprising: first latching means responsive to a first clock signal and a data input for providing a first data output; control means responsive to a control signal, said first data output and a second data input for providing as a controlled data output a replica of said first data output or a replica of said second data input as a function of the control signal; second latching means responsive to a second clock signal and said controlled data output for providing a second data output; and third latching means responsive to a third clock signal and said second data output for providing a third data output.

Claim 3

The shift register stage of claim 1 wherein said first, second and third clock signals are non-overlapping.

Claim 4

The shift register stage of claim 2 wherein for a first mode of operation said control signal controls said control means to provide said replica of said second data input as said controlled data output, said first latching means is not clocked, and said second and third latching means are respectively clocked to function as a master/slave flip-flop.

Claim 5

The shift register stage of claim 3 wherein said second clock signal precedes said third clock signal.

Claim 6

The shift register stage of claim 2 wherein for a second mode of operation said control signal controls said control means to provide said replica of said first data output as said controlled data output, said second and third latching means are clocked as a master/slave flip-flop, and said first and second latching means are subsequently clocked as a master/slave flip-flop.

Claim 7

The shift register stage of claim 2 wherein for a second mode of operation said control signal controls said control means to provide said replica of said first data output as said controlled data output, said first and second latching means are clocked as a master/slave flip-flop, and said second and third latching means are subsequently clocked as a master/slave flip-flop.

Claim 8

The shift register stage of claim 2 wherein for a delay path testing mode of operation said control signal controls said control means to provide said replica of said parallel data input as said controlled data output, said first latching means is not clocked, and said third clock precedes said second clock by a user selected time interval.

Claim 9

The shift register stage of claim 1 wherein said control means comprises a multiplexer.

Claim 10

The shift register stage of claim 1 wherein each of said latching means comprises a clocked D-type latch.

Claim 11

A shift register having a plurality of cascaded shift register stages, including a first stage and a last stage, for selectively accepting a serial data input or a parallel data input and for selectively providing a serial data output or a parallel data output, comprising: respective first latching means for each shift register stage responsive to serial data and for providing respective first data outputs, said first latching means of the first stage selectively responsive to a serial data input to the shift register; respective control means for each shift register stage responsive to said respective first data outputs and to respective parallel data values of a parallel data input to the shift register and for providing as respective controlled data outputs (a) replicas of said respective first data outputs or (b) replicas of said respective parallel data values as a function of a control signal; respective second latching means responsive to said respective controlled data outputs and for providing respective second data outputs; and respective third latching means responsive to said respective second data outputs and for providing respective third data outputs, said respective third data outputs being selectively provided (a) in parallel as a parallel data output of the shift register, or (b) as respective serial data to any subsequent respective first latching means in the shift register, whereby the third data output of the last shift register stage selectively provides a serial data output of the shift register.

Claim 12

A shift register having a plurality of cascaded shift register stages, including a first stage and a last stage, for selectively accepting a serial data input or a parallel data input and for selectively providing a serial data output or a parallel data output, comprising: respective first latching means for each shift register stage responsive to serial data and for providing respective first data outputs, said first latching means of the first stage selectively responsive to a serial data input to the shift register; respective control means for each shift register stage responsive to said respective first data outputs and to respective parallel data values of a parallel data input to the shift register and for providing as respective controlled data outputs (a) replicas of said respective first data outputs or (b) replicas of said respective parallel data values as a function of a control signal; respective second latching means responsive to said respective controlled data outputs and for providing respective second data outputs; and respective third latching means responsive to said respective second data outputs and for providing respective third data outputs, said respective third data outputs being selectively provided (a) in parallel as a parallel data output of the shift register, or (b) as respective serial data to any subsequent respective first latching means in the shift register, whereby the third data output of the last shift register stage selectively provides a serial data output of the shift register.

Claim 13

The shift register of claim 10 wherein (a) all of said respective first latching means are selectively clocked by a first clock signal, (b) all of said respective second latching means are clocked by a second clock signal, and (c) all of said respective third latching means are clocked by a third clock signal; said first, second and third clock signals being non-overlapping.

Claim 14

The shift register of claim 11 wherein for a first mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said parallel data values, said respective first latching means are not clocked, and said respective second and third latching means are clocked to function as respective master/slave flip-flops.

Claim 15

The shift register of claim 11 wherein for a second mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said first data outputs, and said first, second, and third clock signals are selectively phased for loading as a serial data input to the shift register a test vector containing setup values and test values, whereby said respective third latching means are latched to the setup values and said respective second latching means are latched to the test values.

Claim 16

The shift register of claim 13 wherein for said second mode of operation said respective second and third latching means are clocked as master/slave flip-flops, and said respective first and second latching means are subsequently clocked as master/slave flip-flops.

Claim 17

The shift register of claim 13 wherein for said second mode of operation said respective first and second latching means are clocked as master/slave flip-flops, and said respective second and third latching means are subsequently clocked as master/slave flip-flops.

Claim 18

The shift register of claim 11 wherein for a delay path testing mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said parallel data values, said respective first latching means are not clocked, and said third clock signal precedes said second clock by a selectable time interval.

Claim 19

The shift register of claim 10 wherein each of said control means comprises a multiplexer.

Claim 20

The shift register of claim 10 wherein each of said latching means comprises a clocked D-type latch.

Claim 21

An integrated circuit structure comprising: a first shift register having a plurality of cascaded shift register stages, including a first stage and a last stage, for receiving respective parallel inputs and for providing said parallel inputs as respective parallel outputs; a logic network for receiving said parallel outputs of said first shift register and for providing logic network outputs in response thereto; a second shift register having a plurality of cascaded shift register stages, including a first stage and a last stage, for receiving said logic network outputs as respective parallel inputs and for providing said parallel inputs as respective parallel outputs; respective first latching means for each shift register stage responsive to serial data and for providing respective first data outputs, said first latching means of the respective first stages selectively responsive to respective serial data inputs to the respective shift registers, respective control means for each shift register stage responsive to said respective first data outputs and to respectively associated shift register parallel inputs and for providing as respective controlled data outputs (a) replicas of said respective first data outputs or (b) replicas of said respectively associated shift register parallel inputs, as a function of a control signal; respective second latching means responsive to said respective controlled data outputs and for providing respective second data outputs; and respective third latching means responsive to said respective second data outputs and for providing respective third data outputs, said respective third data outputs being selectively provided (a) in parallel as respective shift register parallel outputs, or (b) as respective serial data to any subsequent respective first latching means in the shift register, whereby the third data output of the last shift register stage selectively provides a serial data output of the shift register.

Claim 22

An integrated circuit structure comprising: a first shift register having a plurality of cascaded shift register stages, including a first stage and a last stage, for receiving respective parallel inputs and for providing said parallel inputs as respective parallel outputs; a logic network for receiving said parallel outputs of said first shift register and for providing logic network outputs in response thereto; a second shift register having a plurality of cascaded shift register stages, including a first stage and a last stage, for receiving said logic network outputs as respective parallel inputs and for providing said parallel inputs as respective parallel outputs; respective first latching means for each shift register stage responsive to serial data and for providing respective first data outputs, said first latching means of the respective first stages selectively responsive to respective serial data inputs to the respective shift registers, respective control means for each shift register stage responsive to said respective first data outputs and to respectively associated shift register parallel inputs and for providing as respective controlled data outputs (a) replicas of said respective first data outputs or (b) replicas of said respectively associated shift register parallel inputs, as a function of a control signal; respective second latching means responsive to said respective controlled data outputs and for providing respective second data outputs; and respective third latching means responsive to said respective second data outputs and for providing respective third data outputs, said respective third data outputs being selectively provided (a) in parallel as respective shift register parallel outputs, or (b) as respective serial data to any subsequent respective first latching means in the shift register, whereby the third data output of the last shift register stage selectively provides a serial data output of the shift register.

Claim 23

The integrated circuit structure of claim 19 wherein (a) said respective first latching means are selectively clocked by a first clock signal, (b) said respective second latching means are clocked by a second clock signal, and (c) said respective third latching means are clocked by a third clock signal; said first, second and third clock signals being non-overlapping.

Claim 24

The integrated circuit structure of claim 20 wherein for a first mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said shift register parallel inputs, said respective first latching means are not clocked, and said respective second and third latching means are clocked to function as respective master/slave flip-flops.

Claim 25

The integrated circuit structure of claim 20 wherein for a second mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said first data outputs; and wherein said first, second, and third clock signals are selectively phased for loading as a serial data input to said first register shift register a test vector containing setup values and test values, whereby said respective third latching means of said first register are latched to the setup values and said respective second latching means of said first register are latched to the test values.

Claim 26

The integrated circuit structure of claim 22 wherein for said second mode of operation said respective second and third latching means are clocked as master/slave flip-flops, and said respective first and second latching means are subsequently clocked as master/slave flip-flops.

Claim 27

The integrated circuit structure of claim 22 wherein for said second mode of operation said respective first and second latching means are clocked as master/slave flip-flops, and said respective second and third latching means are subsequently clocked as master/slave flip-flops.

Claim 28

The integrated circuit structure of claim 22 wherein for an AC test mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said shift register parallel inputs, said respective first latching means are not clocked, and said third clock signal precedes said second clock by a selectable time interval, whereby said test values stored in said first shift register are applied as said logic network inputs to said logic network pursuant to said third clock signal and the responses of said logic network are provided as said logic network outputs which are stored in said second shift register pursuant to said second clock signal.

Claim 29

The integrated circuit structure of claim 20 wherein for a second mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said first data outputs; and wherein said first, second, and third clock signals are selectively phased for loading as serial data input to said first and second register shift registers respective test vectors containing setup values and test values; whereby said respective third latching means are latched to the setup values and said respective second latching means are latched to the test values.

Claim 30

The integrated circuit structure of claim 26 wherein for said second mode of operation said respective second and third latching means are clocked as master/slave flip-flops, and said respective first and second latching means are subsequently clocked as master/slave flip-flops.

Claim 31

The integrated circuit structure of claim 26 wherein for said second mode of operation said respective first and second latching means are clocked as master/slave flip-flops, and said respective second and third latching means are subsequently clocked as master/slave flip-flops.

Claim 32

The integrated circuit structure of claim 26 wherein for an AC test mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said shift register parallel inputs, said respective first latching means are not clocked, and said third clock signal precedes said second clock by a selectable time interval, whereby said test values stored in said first and second shift registers are respectfully applied as said logic network inputs to said logic network and as inputs to a further logic network pursuant to said third clock signal and whereby the responses of said logic network are provided as said logic network outputs which are stored in said second shift register pursuant to said second clock signal.

Claim 33

The integrated circuit structure of claim 20 wherein for a delay path testing mode of operation said control signal controls said respective control means to provide as said respective controlled data outputs said replicas of said shift register parallel inputs, said respective first latching means are not clocked, and said third clock signal prcedes said second clock by a selectable time interval.

Claim 34

The integrated circuit structure of claim 19 wherein each of said control means comprises a multiplexer.

Claim 35

The integrated circuit structure of claim 19 wherein each of said latching means comprises a clocked D-type latch.