US3786440A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital data storage with equal input and output data rate, but variable memory shift rate
Assignee: General Dynamics Corp
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Filing: 1973-01-26
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Granted: 1974-01-15
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Expires: 1993-01-26
Abstract
Abstract The storage capacity or length of a memory consisting of shift registers which may only be available in certain discrete bit lengths is controlled or programmed by shifting data from each stage of an input serial to parallel shift register into different ones of the memory shift registers and then transferring the data from the output stages of the memory registers into an output parallel to serial shift register. The ratio, between the number of clock pulses which shift the data into and out of the input and output registers and number of clock pulses which shift the data in the memory registers, is changed so as to alter the fan out of data from the input shift register into the memory registers. The storage capacity or length of the memory can be changed or programmed during storage operations so as to have any length up to and including the storage capacity of all of the memory registers and any additional buffer registers which may be associated therewith.
Inventors
- 👤 G Toyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:38
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/08; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
107 words
The method of storing digital data which comprises a. sequentially presenting a plurality of different bits of a series of bits for storage at the inputs of a plurality of storage devices each of which has storage for a plurality of bits in series; b. advancing said bits stored in said devices sequentially in each of said devices at a predetermined rate less than the rate of sequential presentation; c. deriving a series of bits each from the output of a different one of said devices; and d. advancing said derived series of bits in the order in which derived and at said rate of sequential presentation.
Claim 2
Independent Claim
107 words
The method of storing digital data which comprises a. sequentially presenting a plurality of different bits of a series of bits for storage at the inputs of a plurality of storage devices each of which has storage for a plurality of bits in series; b. advancing said bits stored in said devices sequentially in each of said devices at a predetermined rate less than the rate of sequential presentation; c. deriving a series of bits each from the output of a different one of said devices; and d. advancing said derived series of bits in the order in which derived and at said rate of sequential presentation.
Claim 3
Dependent Claim
28 words
The invention as set forth in claim 1 including the step of alternately advancing said bits at a second predetermined rate and at said first named predetermined rate.
Claim 4
Dependent Claim
78 words
The invention as set forth in claim 2 wherein said step of advancing at said first and second rates are carried on for first predetermined number of times at said first rate and a second number of predetermined times at said second rate where said second number of predetermined times Equals the difference between the number of said plurality of bits in series for which each of said devices has storage and said first predetermined number of times.
Claim 5
Dependent Claim
32 words
The invention as set forth in claim 3 including the step of changing said first and second predetermined numbers while said bits are presented to the inputs of said devices for storage.
Claim 6
Dependent Claim
55 words
The invention as set forth in claim 1 including the step of successively presenting each of the bits which constitute said plurality to the input of another device having storage of said first named series of bits, and successively advancing each of said presented bits in said other device at said rate of sequential presentation.
Claim 7
Dependent Claim
139 words
The invention as set forth in claim 5 including the step of presenting words consisting of a plurality of bits in parallel, each to the input of a separate one of said other devices for providing a plurality of said first named series of bits, sequentially presenting in parallel each of said plurality of said first named series of bits to the inputs of said plurality of said storage devices which corresponds to different ones of said plurality of first named series of bits, advancing said bits stored in each of said devices at said predetermined rate, deriving separate series of bits from the outputs of each of said different groups of devices, and advancing each of said derived series of bits in the order in which derived and at said rate of presentation to read out said words.
Claim 8
Independent Claim
157 words
A system for storing digital data which comprises first means for storing a plurality of consecutive bits of said data in series, a plurality of means each for storing a plurality of bits in series, means for entering at a first rate, different ones of said bits from said first storage means into the input of different ones of said second storage means, means for advancing said bits in each of said plurality of storing means from the input to the output thereof at said first rate, means for advancing said bits, said first storing means at a second rate greater than said first rate, second means for storing a plurality of consecutive bits in series, means for entering bits from the outputs of different ones of said plurality of storing means in series in said second storing means, and means for reading out said bits stored in said second storing means consecutively at said second rate.
Claim 9
Independent Claim
157 words
A system for storing digital data which comprises first means for storing a plurality of consecutive bits of said data in series, a plurality of means each for storing a plurality of bits in series, means for entering at a first rate, different ones of said bits from said first storage means into the input of different ones of said second storage means, means for advancing said bits in each of said plurality of storing means from the input to the output thereof at said first rate, means for advancing said bits, said first storing means at a second rate greater than said first rate, second means for storing a plurality of consecutive bits in series, means for entering bits from the outputs of different ones of said plurality of storing means in series in said second storing means, and means for reading out said bits stored in said second storing means consecutively at said second rate.
Claim 10
Dependent Claim
15 words
The invention as set forth in claim 7 including means for changing said first rate.
Claim 11
Dependent Claim
38 words
The invention as set forth in claim 8 wherein said rate changing means includes means operative to alternately change said first rate after first and second predetermined numbers of bits are entered into said plurality of storing means.
Claim 12
Dependent Claim
46 words
The invention as set forth in claim 9 wherein said plurality of storing means each has storage for N bits and wherein said changing means includes means for changing said rate after B and again after N-B bits are entered into said plurality of storing means.
Claim 13
Dependent Claim
60 words
The invention as set forth in claim 7 wherein said first storing means is a shift register having M stages each for a separate one of said plurality of consecutive bits, means for said bits into the first of said M stages, and means for advancing said bits from between successive ones of said M stages at said second rate.
Claim 14
Dependent Claim
48 words
The invention as set forth in claim 11 wherein each of said plurality of storing means is a separate shift register having storage for N bits, different ones of said M stages being connected to the first or input stage of different ones of said plurality of registers.
Claim 15
Dependent Claim
70 words
The invention as set forth in claim 12 including an M stage buffer register connected between said first storing means and said input stages of said plurality of N stage storing means shift registers, and means for transferring the bits in said M stage first register into said M stage buffer register and then from said M stage buffer register to said N stage register inputs at saId first rate.
Claim 16
Dependent Claim
94 words
The invention as set forth in claim 12 including an M stage output shift register, each stage of which being connected to Nth or output stage of different ones of said plurality of N stage shift register, means for entering the bits stored in said output stages into different ones of the stages of said output register at said first rate, and means for advancing said bits consecutively between the stages of said output register at said second rate, read out from said system being provided at the Mth stage of said output register.
Claim 17
Dependent Claim
57 words
The invention as set forth in claim 14 wherein said means for advancing said bits at said first rate includes means for counting clock pulses at said second rate to provide clock pulses at said first rate and means for applying said clock pulses as shift pulses to each of said plurality of N stage shift registers.
Claim 18
Dependent Claim
48 words
The invention as set forth in claim 15 including means for changing said first rate including means for presetting said counter after said counter counts a predetermined number of said second rate clock pulses for a predetermined number of successive first clock pulses at said changed first rate.
Claim 19
Dependent Claim
121 words
The invention as set forth in claim 16 wherein said presetting means includes a second counter which counts N clock pulses and then recycles, means responsive to the count stored in said second counter when said count reaches B, a number less than N, for providing a control signal until said second counter reaches a count of N, and means for presetting said first counter to provide said each of second clock pulses after a number L which is equal or less than M of said first clock pulses when said control signal is present and to provide each of said second clock pulses after a number less than L of said first clock pulses when said control signal is absent.
Claim 20
Dependent Claim
176 words
The invention as set forth in claim 17 wherein said system is organized to provide storage for words of said digital data and includes a plurality of said M stage first storing means registers each for a separate bit of said words, a plurality of groups of said N stage shift registers each corresponding to a different one of said M stage first storing means registers, the input stages of said N stage register being connected to different ones of the M stages of the M stage first storing means register corresponding thereto, and a plurality of M stage output registers each corresponding to a different one of the groups of N stage shift registers, the output stages of each group of N stage shift registers each being connected to a different stage of the M stage output shift register corresponding thereto, said second rate clock pulses being applied to all said M stage first storing means and output registers and said first rate clock pulses being applied to all of said N stage shift registers.
References Cited (Backward Citations)
US3292156A
Cited
US3521245A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-14 | 1977-07-16 | 1978-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-14 | 1981-07-16 | 1982-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-14 | 1985-07-16 | 1986-01-15 | $7700.00 | Window Closed / Lapsed |