US4277699A
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US
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Latch circuit operable as a D-type edge trigger
Assignee: International Business Machines Corp
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Filing: 1979-07-26
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Granted: 1981-07-07
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Expires: 1999-07-26
Abstract
Abstract A shift register latch circuit (FIG. 1) comprised of a polarity hold latch 1 connected to a set/reset latch 2. The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input S to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a `D` type edge trigger by connecting the clock input +B of the set/reset latch 2 to the clock -C supplied to the polarity hold latch 1. By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.
Inventors
- 👤 David J. Brown
- 👤 Ronald G. Walther
- 👤 Thomas W. Williams
- 👤 Michael D. Wrigglesworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:04
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G06; G06F; G06F7/00; G11; G11C; G11C19/00; G11C19/14; G11C19/28; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
286 words
A shift register latch circuit for use in an integrated circuit conforming to Level Sensitive Scan Design (LSSD), said shift register latch circuit comprising: a first AND/INVERT circuit having a first input for receiving a SCAN IN input, a second input for receiving a first clock pulse train, and an output; a second AND/INVERT circuit having a first input for receiving a data input, a second input for receiving a second clock pulse train, and an output; a third AND/INVERT circuit having a first input for receiving the complement of said second clock pulse train, a second input for receiving the complement of said first clock pulse train, a third input, and an output; an Inverter circuit having an input and output; a fourth AND/INVERT circuit having a first input connected in common to said output of said first AND/INVERT circuit, said output of said second AND/INVERT circuit, said output of said third AND/INVERT circuit and said input of said Inverter circuit, a second input, and an output; a fifth AND/INVERT circuit having a first input connected in common to said output of said Inverter circuit and said third input of said third AND/INVERT circuit, a second input connected in common with said second input of said fourth AND INVERT circuit for receiving a third clock pulse train, and an output; a sixth AND/INVERT circuit having a first input connected to said output of said fourth AND/INVERT circuit, a second input, and an output; and a seventh AND/INVERT circuit having a first input connected to said output of said sixth AND/INVERT circuit, a second input connected to said output of said fifth AND/INVERT circuit and an output connected to said second input of said sixth AND/INVERT.
Claim 2
Dependent Claim
286 words
A shift register latch circuit for use in an integrated circuit conforming to Level Sensitive Scan Design (LSSD), said shift register latch circuit comprising: a first AND/INVERT circuit having a first input for receiving a SCAN IN input, a second input for receiving a first clock pulse train, and an output; a second AND/INVERT circuit having a first input for receiving a data input, a second input for receiving a second clock pulse train, and an output; a third AND/INVERT circuit having a first input for receiving the complement of said second clock pulse train, a second input for receiving the complement of said first clock pulse train, a third input, and an output; an Inverter circuit having an input and output; a fourth AND/INVERT circuit having a first input connected in common to said output of said first AND/INVERT circuit, said output of said second AND/INVERT circuit, said output of said third AND/INVERT circuit and said input of said Inverter circuit, a second input, and an output; a fifth AND/INVERT circuit having a first input connected in common to said output of said Inverter circuit and said third input of said third AND/INVERT circuit, a second input connected in common with said second input of said fourth AND INVERT circuit for receiving a third clock pulse train, and an output; a sixth AND/INVERT circuit having a first input connected to said output of said fourth AND/INVERT circuit, a second input, and an output; and a seventh AND/INVERT circuit having a first input connected to said output of said sixth AND/INVERT circuit, a second input connected to said output of said fifth AND/INVERT circuit and an output connected to said second input of said sixth AND/INVERT.
Claim 3
Dependent Claim
48 words
A shift register latch circuit as recited in claim 1 wherein said second input of said fourth AND/INVERT circuit and said second input of said fifth AND/INVERT circuit are connected in common to the complement of said second clock pulse train rather than said third clock pulse train.
Claim 4
Dependent Claim
231 words
A shift register latch circuit for use in an integrated circuit conforming to Level Sensitive Scan Design (LSSD), said shift register latch circuit comprising: a first AND/OR/INVERT circuit having a first input for receiving data, a second input for receiving a first clock pulse train, a third input for receiving the complement of said first clock pulse train, a fourth input, and an output; a second AND/OR/INVERT circuit having a first input connected to the output of said first AND/OR/INVERT circuit, a second input for receiving the complement of a second clock pulse train, a third input for receiving a SCAN IN input, a fourth input for receiving said second clock pulse train, and an output; an Inverter circuit having an input and an output; a third AND/OR/INVERT circuit having a first input connected in common to said fourth input of said first AND/OR/INVERT circuit, said input of said Inverter circuit and said output of said second AND/OR/INVERT circuit, a second input, a third input, and an output; a fourth AND/OR/INVERT circuit having a first input connected to said output of said third AND/OR/INVERT circuit, a second input connected to the output of said Inverter circuit, a third input connected in common to said second input of said third AND/OR/INVERT circuit for receiving a third clock pulse train, and an output connected to said third input of said third AND/OR/INVERT circuit.
Claim 5
Dependent Claim
231 words
A shift register latch circuit for use in an integrated circuit conforming to Level Sensitive Scan Design (LSSD), said shift register latch circuit comprising: a first AND/OR/INVERT circuit having a first input for receiving data, a second input for receiving a first clock pulse train, a third input for receiving the complement of said first clock pulse train, a fourth input, and an output; a second AND/OR/INVERT circuit having a first input connected to the output of said first AND/OR/INVERT circuit, a second input for receiving the complement of a second clock pulse train, a third input for receiving a SCAN IN input, a fourth input for receiving said second clock pulse train, and an output; an Inverter circuit having an input and an output; a third AND/OR/INVERT circuit having a first input connected in common to said fourth input of said first AND/OR/INVERT circuit, said input of said Inverter circuit and said output of said second AND/OR/INVERT circuit, a second input, a third input, and an output; a fourth AND/OR/INVERT circuit having a first input connected to said output of said third AND/OR/INVERT circuit, a second input connected to the output of said Inverter circuit, a third input connected in common to said second input of said third AND/OR/INVERT circuit for receiving a third clock pulse train, and an output connected to said third input of said third AND/OR/INVERT circuit.
Claim 6
Dependent Claim
48 words
A shift register latch circuit as recited in claim 3 wherein said third input of said fourth AND/OR/INVERT circuit and said second input of said third AND/OR/INVERT circuit are connected in common to the complement of said first clock pulse train rather than said third clock pulse train.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-06 | 1985-01-05 | 1985-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-06 | 1989-01-05 | 1989-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-06 | 1993-01-05 | 1993-07-07 | $7700.00 | Window Closed / Lapsed |