Biphase digital look-ahead demodulating method and apparatus

Claim 1

A method for decoding digitally encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, successive transitions over a period of time equal to one transmitted clock or bit cycle represent one transmitted clock cycle and a transmitted data signal of one polarity, and successive transitions over one bit cycle with an additional transition occurring mid-way through the bit cycle represent a transmitted clock cycle and a transmitted data signal of the opposite polarity, comprising the steps of: sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; detecting whether or not a transition of the transmission signal occurred within said sample; timing the difference between successive transitions; decoding each transition as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of a bit cycle wherein a transition occurring before a 3/4 bit time interval after the start of a new bit cycle is decoded as a mid-bit transition while a transition occurring after the 3/4 bit time interval is decoded as the start of a new bit cycle; and deferring the decoding decision for a first transition which occurs within a sample time containing the 3/4 bit time interval after the start of a new bit cycle until a second transition occurs, at which time the first transition is decoded as a mid-bit transition if the second transition occurs before a specified time interval after the first transition and decoded as the start of a new bit cycle otherwise.

Claim 2

A method for decoding digitally encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, successive transitions over a period of time equal to one transmitted clock or bit cycle represent one transmitted clock cycle and a transmitted data signal of one polarity, and successive transitions over one bit cycle with an additional transition occurring mid-way through the bit cycle represent a transmitted clock cycle and a transmitted data signal of the opposite polarity, comprising the steps of: sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; detecting whether or not a transition of the transmission signal occurred within said sample; timing the difference between successive transitions; decoding each transition as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of a bit cycle wherein a transition occurring before a 3/4 bit time interval after the start of a new bit cycle is decoded as a mid-bit transition while a transition occurring after the 3/4 bit time interval is decoded as the start of a new bit cycle; and deferring the decoding decision for a first transition which occurs within a sample time containing the 3/4 bit time interval after the start of a new bit cycle until a second transition occurs, at which time the first transition is decoded as a mid-bit transition if the second transition occurs before a specified time interval after the first transition and decoded as the start of a new bit cycle otherwise.

Claim 6

An apparatus for decoding digitally encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, successive transitions over a period of time equal to one transmitted clock or bit cycle represent one transmitted clock cycle and a transmitted data signal of one polarity, and successive transitions over one bit cycle with an additional transition occurring mid-way through the bit cycle represent a transmitted clock cycle and a transmitted data signal of the opposite polarity, comprising: means for sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; means for detecting whether or not a transition of the transmission signal occurred within said sample; means for timing the difference between successive transitions; means for decoding each transition as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of a bit cycle wherein a transition occurring before a 3/4 bit time interval after the start of a new bit cycle is decoded as a mid-bit transition, while a transition occurring after the 3/4 bit time interval is decoded as the start of a new bit cycle; and means for deferring the decoding decision for a first transition which occurs within a sample time containing the 3/4 bit time interval after the start of a new bit cycle until a second transition occurs, at which time the first transition is decoded as a mid-bit transition if the second transition occurs before a specified time interval after the first transition and decoded as the start of a new bit cycle otherwise.

Claim 7

An apparatus for decoding digitally encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, successive transitions over a period of time equal to one transmitted clock or bit cycle represent one transmitted clock cycle and a transmitted data signal of one polarity, and successive transitions over one bit cycle with an additional transition occurring mid-way through the bit cycle represent a transmitted clock cycle and a transmitted data signal of the opposite polarity, comprising: means for sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; means for detecting whether or not a transition of the transmission signal occurred within said sample; means for timing the difference between successive transitions; means for decoding each transition as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of a bit cycle wherein a transition occurring before a 3/4 bit time interval after the start of a new bit cycle is decoded as a mid-bit transition, while a transition occurring after the 3/4 bit time interval is decoded as the start of a new bit cycle; and means for deferring the decoding decision for a first transition which occurs within a sample time containing the 3/4 bit time interval after the start of a new bit cycle until a second transition occurs, at which time the first transition is decoded as a mid-bit transition if the second transition occurs before a specified time interval after the first transition and decoded as the start of a new bit cycle otherwise.

Claim 10

A method for decoding digitally encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, a zero during the first half of the bit cycle and a one during the second half of the bit cycle represents a data signal of one polarity, and a one during the first half of the bit cycle with a zero during the second half represents a data signal of the opposite polarity, comprising the steps of: sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; detecting whether or not a transition of the transmission signal occurred within said sample; timing the difference between successive transitions; decoding each transition as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of a bit cycle wherein a transition occurring before a 3/4 bit time interval after a mid-bit transition is detected is decoded as the start of a new bit cycle, while a transition occurring after the 3/4 bit time interval is decoded as a mid-bit transition; and deferring the decoding decision for a first transition occurring after a mid-bit transition which occurs within a sample time containing the 3/4 bit time interval after a mid-bit transition is detected until a second transition occurs, at which time the first transition is decoded as the start of a new bit cycle if the second transition occurs before a specified time interval after the first transition and decoded as a mid-bit transition otherwise.

Claim 11

A method for decoding digitally encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, a zero during the first half of the bit cycle and a one during the second half of the bit cycle represents a data signal of one polarity, and a one during the first half of the bit cycle with a zero during the second half represents a data signal of the opposite polarity, comprising the steps of: sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; detecting whether or not a transition of the transmission signal occurred within said sample; timing the difference between successive transitions; decoding each transition as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of a bit cycle wherein a transition occurring before a 3/4 bit time interval after a mid-bit transition is detected is decoded as the start of a new bit cycle, while a transition occurring after the 3/4 bit time interval is decoded as a mid-bit transition; and deferring the decoding decision for a first transition occurring after a mid-bit transition which occurs within a sample time containing the 3/4 bit time interval after a mid-bit transition is detected until a second transition occurs, at which time the first transition is decoded as the start of a new bit cycle if the second transition occurs before a specified time interval after the first transition and decoded as a mid-bit transition otherwise.

Claim 15

An apparatus for decoding digitally encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, a zero during the first half of the bit cycle and a one during the second half represents a data signal of the opposite polarity, comprising: means for sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; means for detecting whether or not a transition of the transmission signal occurred within said sample; means for timing the difference between successive transitions; means for decoding each transition as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of a bit cycle wherein a transition occurring before a 3/4 bit time interval after a mid-bit transition is detected is decoded as the start of a new bit cycle, while a transition occurring after the 3/4 bit time interval is decoded as a mid-bit transition; and means for deferring the decoding decision for a first transition occurring after a mid-bit transition which first transition is detected within a sample time containing the 3/4 bit time interval after the mid-bit transition until a second transition occurs, at which time the first transition is decoded as the start of a new bit cycle if the second transition occurs before a specified time interval after the first transition and decoded as a mid-bit transition otherwise.

Claim 16

An apparatus for decoding digitally encoded transmission signals where transitions within the transmission signal represent a combination of transmitted clock and data signals, the frequency of the transmitted clock signal is known, a zero during the first half of the bit cycle and a one during the second half represents a data signal of the opposite polarity, comprising: means for sampling the transmission signal at a rate equal to some multiple of the transmitted clock frequency; means for detecting whether or not a transition of the transmission signal occurred within said sample; means for timing the difference between successive transitions; means for decoding each transition as the most probable of either the start of a new bit cycle or a mid-bit transition according to the known length of a bit cycle wherein a transition occurring before a 3/4 bit time interval after a mid-bit transition is detected is decoded as the start of a new bit cycle, while a transition occurring after the 3/4 bit time interval is decoded as a mid-bit transition; and means for deferring the decoding decision for a first transition occurring after a mid-bit transition which first transition is detected within a sample time containing the 3/4 bit time interval after the mid-bit transition until a second transition occurs, at which time the first transition is decoded as the start of a new bit cycle if the second transition occurs before a specified time interval after the first transition and decoded as a mid-bit transition otherwise.