Data converting and clock pulse generating system

Claim 3

A data converting system comprising: first input means for receiving split phase Manchester encoded binary data having a first waveform wherein each bit of a first value is represented by a transition from a first logic level to a second logic level at mid bit time and each bit of a second value is represented by a transition from said second logic level to said first logic level at mid bit time, said first waveform further including level transitions at the time between successive bit times associated with bits having the same value; second input means for receiving a second waveform complementary to said first waveform; a first transition detector for providing a first pulse for each transition from said first level to said second level in said first waveform; a second transition detector for providing a second pulse for each transition from said first level to said second level in said second waveform; bistable means; control means, including pulse generating means and delay means, responsive to said first and second pulses for driving said bistable means to a first stable state in response to each first pulse from said first transition detector which occurs more than one-half bit time after the occurrence of the most recent second pulse from said second transition detector and for driving said bistable means to a second stable state in response to each second pulse which occurs more than one-half bit time after the occurrence of the most recent first pulse from said first detector; and said control means including first, second, third and fourth gates, each having a control input connected to the output from said delay means, means connecting the output of said first detector to another input of each of said first and third gates, means connecting the output of said second detector to another input of each of said second and fourth gates, each gate providing an output pulse in response to a pulse supplied thereto on its said another input only when its control input is at an enabling level, means for applying the output from said first and second gates to said pulse generating means to provide an output pulse in response to a pulse from either said first or second gate, and means for applying each output pulse from said pulse generating means to said delay means to apply to the control input of each of said gates a disabling level for a period of time not less than one-half bit time.

Claim 4

A data converting system comprising: first input means for receiving split phase Manchester encoded binary data having a first waveform wherein each bit of a first value is represented by a transition from a first logic level to a second logic level at mid bit time and each bit of a second value is represented by a transition from said second logic level to said first logic level at mid bit time, said first waveform further including level transitions at the time between successive bit times associated with bits having the same value; second input means for receiving a second waveform complementary to said first waveform; a first transition detector for providing a first pulse for each transition from said first level to said second level in said first waveform; a second transition detector for providing a second pulse for each transition from said first level to said second level in said second waveform; bistable means; control means, including pulse generating means and delay means, responsive to said first and second pulses for driving said bistable means to a first stable state in response to each first pulse from said first transition detector which occurs more than one-half bit time after the occurrence of the most recent second pulse from said second transition detector and for driving said bistable means to a second stable state in response to each second pulse which occurs more than one-half bit time after the occurrence of the most recent first pulse from said first detector; and said control means including first, second, third and fourth gates, each having a control input connected to the output from said delay means, means connecting the output of said first detector to another input of each of said first and third gates, means connecting the output of said second detector to another input of each of said second and fourth gates, each gate providing an output pulse in response to a pulse supplied thereto on its said another input only when its control input is at an enabling level, means for applying the output from said first and second gates to said pulse generating means to provide an output pulse in response to a pulse from either said first or second gate, and means for applying each output pulse from said pulse generating means to said delay means to apply to the control input of each of said gates a disabling level for a period of time not less than one-half bit time.

Claim 5

The system as recited in claim 1 wherein said resistive means includes a diffused resistive region in the semiconductor substrate on which said field effect transistor is formed.

Claim 6

The system as recited in claim 1 wherein the drain electrode of the field effect transistor of one of said Control gates is coupled to the drain electrode of the field effect transistor of another of said control gates and the source electrode of the field effect transistor of said one of said control gates is coupled to the source electrode of the field effect transistor of said another of said control gates, the gate electrode of the field effect transistor of said one of said control gates being coupled to said first transition detector means, the gate electrode of the field effect transistor of said another of said control gates being coupled to said second transition detector means, and wherein a resistor is coupled between the intercoupled drain electrodes and said first power supply terminal, and the source-drain path of a further metal oxide semiconductor field effect transistor is coupled between the intercoupled source electrodes and said second power supply terminal, the gate electrode of said further field effect transistor being coupled to the drain electrode of the field effect transistor of said delay means.

Claim 7

The system as recited in claim 4 wherein said pulse generating means includes first, second and third metal oxide semiconductor field effect transistors each having a source electrode, a drain electrode and a gate electrode, the gate electrodes of said first and said third field effect transistors being coupled to the intercoupled drain electrodes of the field effect transistors of said one and said another control gates, the source electrodes of said first and third field effect transistors being coupled to said second power supply terminal, a resistor coupled between the drain electrode of said first field effect transistor and said first power supply terminal, the gate electrode of said second field effect transistor being coupled to the drain electrode of said first field effect transistor, the drain electrode electrode of said second field effect transistor being coupled to said first power supply terminal, the source electrode of said second field effect transistor being coupled to the drain electrode of said third field effect transistor and to a terminal of said resistive means electrically remote from the gate electrode of the field effect transistor of said delay means.

Claim 8

The system as recited in claim 4 wherein the source electrode of the field effect transistor of a third of said control gates is coupled to the source electrode of the field effect transistor of a fourth of said control gates, the drain electrodes of the field effect transistors of said third and fourth control gates each being resistively coupled to said first power supply terminal, the gate electrode of the field effect transistor of said third control gate being coupled to said first transition detector means, the gate electrode of the field effect transistor of said fourth control gate being coupled to said second transition detector means, and the intercoupled source electrodes of the field effect transistors of said third and fourth control gates being coupled to the drain electrode of the field effect transistor of said delay means.

Claim 9

The system as recited in claim 6 and further comprising: a bistable circuit including two interconnected metal oxide semiconductor field effect transistors, one input to said bistable circuit being coupled to the drain electrode of the field effect transistor of said third control gate and the other input to said bistable circuit being coupled to the drain electrode of the field effect transistor of said fourth control gate.

Claim 10

The system as recited in claim 1 wherein each of said transition detector means comprises: a pair of metal oxide semiconductor field effect transistors and an additional metal oxide semiconductor field effect transistor, the respective drain electrodes of said pair of transistors being coupled together and the respective source electrodes of said pair of transistors being coupled together, a resistor coupled between the drain electrodes of said pair of transistors and said first power supply terminal, the Source electrodes of said pair of transistors and of said additional transistor being coupled to said second power supply terminal, the gate electrode of one of said pair of transistors being coupled to the drain electrode of said additional transistor and being resistively coupled to a third power supply terminal, an input terminal coupled to the gate electrode of the other of said pair of transistors and coupled via resistive delay means to the gate electrode of said additional transistor, and means for coupling the drain electrodes of said pair of transistors to at least one of said control gates.

Claim 11

The system as recited in claim 2 wherein said delay means includes a metal oxide semiconductor field effect transistor having a source electrode, a drain electrode and a gate electrode, said drain electrode being resistively coupled to a first power supply terminal and to the control input to said first, second, third and fourth gates, said source electrode being coupled to a second power supply terminal, and a resistor coupled between said gate electrode and the output of said pulse generating means.

Claim 12

The system as recited in claim 9 wherein each of said first, second, third and fourth gates includes a metal oxide semiconductor field effect transistor having a source electrode, a drain electrode and a gate electrode, the source electrodes of each of said field effect transistors being coupled together, the drain electrodes of each of said field effect transistors being coupled to said first power supply terminal, the gate electrodes of the field effect transistors of said first and third gates being coupled to the output of said first detector, the gate electrodes of the field effect transistors of said second and fourth gates being coupled to the output of said second detector, and wherein the source-drain path of a further metal oxide semiconductor field effect transistor is coupled between the intercoupled source electrodes and said second power supply terminal, the gate electrode of said further field effect transistor being coupled to the drain electrode of the field effect transistor of said delay means.