Self synchronizing clock derivation circuit for double frequency encoded digital data

Claim 2

A self-synchronizing circuit for reconstructing the timing information encoded in an incoming double frequency transition-event waveform, said incoming waveform characterized as including both guaranteed and non-quaranteed transitions, said incoming waveform further characterized as having a bit cell duration of T, said circuit arrangement comprising: delay line means, responsive to said incoming waveform, said delay line means for generating a set of at least two delayed versions of said incoming waveform; detecting means, responsive to said incoming waveform and said set of delayed versions of said incoming waveform, said detecting means for detecting each transition in said incoming waveform and producing first and second transition waveforms, each of said transition waveforms identifying each transition in said incoming waveform; isolating means, connected to said detecting means, said isolating means for isolating out the set of guaranteed transitions in said detected transitions, whereby at least one set of timing information is reconstructed; and synchronizing means, connected to an output of said delay line means and said isolating means and responsive to said incoming waveform, said synchronizing means for assuring that said isolating means is properly synchronized with said incoming waveform.

Claim 3

The circuit in accordance with claim 1 wherein said synchronizing means includes: a third logical exclusive OR gate receiving its inputs from said incoming waveform and a second one of said set of delayed versions of said incoming waveform; and a third logical NAND gate receiving its inputs from the output of said third exclusive OR gate and an output of said isolating means, the output of said third NAND gate providing an input to said isolating means.

Claim 4

The circuit in accordance with claim 2 wherein said set of delayed versions of said incoming waveform includes three delayed versions of said incoming waveform, said first, second, and third delayed versions corresponding to the incoming waveform delayed by 1/4 T, 1/2 T and 3/4 T, respectively.

Claim 5

The circuit in accordance with claim 2 wherein said detecting means includes: a first logical exclusive OR gate receiving its inputs from said incoming waveform and a first one of said set of delayed versions of said incoming waveform; and a second logical exclusive OR gate receiving its inputs from said second one and a third one of said set of delayed versions of said incoming waveform.

Claim 6

The circuit in accordance with claim 4 wherein said isolating means includes: a logical NOR gate receiving its inputs from the output of said first and said second exclusive OR gates; a logical flip-flop receiving its clocking input from the output of said logical NOR gate; and a first logical NAND gate receiving its inputs from the output of said first exclusive OR gate and the true output of said flip-flop, whereby a first set of said timing information is reconstructed at the output of said first NAND gate.

Claim 7

The circuit in accordance with claim 5 wherein said isolating means further includes a second logical NAND gate receiving its inputs from the output of said second exclusive OR gate and the false output of said flip-flop, whereby a second set of said timing information is reconstructed at the output of said second NAND gate.

Claim 8

The circuit in accordance with claim 5 wherein said logical flip-flop is a D-type, negative edge triggered flip-flop.

Claim 9

The circuit in accordance with claim 7 wherein the output of said third NAND gate is connected as the D input to said flip-flop and the true output of said flip-flop is an input to said third NAND gate.

Claim 10

The circuit in accordance with claim 1 wherein said synchronizing means includes: third detecting means, responsive to said incoming waveform and a second one of said set of delayed versions of said incoming waveform, said third detecting means for comparing said incoming waveform with said second delayed version of said incoming waveform; and initializing means, connected to said third detecting means and responsive to said isolating means, said initializing means for initializing said isolating means to isolate the next received guaranteed transition in said incoming waveform.

Claim 11

The circuit in accordance with claim 9 wherein said detecting means includes: first detecting means, responsive to said incoming waveform and a first one of said set of delayed versions of said incoming waveform, said first detecting means for generating said first transition waveform, said first transition waveform providing a pulse coincident with the start of each transition in said incoming waveform; and second detecting means, responsive to the second and a third of said set of delayed versions of said incoming waveform, said second detecting means for generating said second transition waveform, said second transition waveform corresponding to the first transition waveform delayed by a fixed time interval, the second transition waveform providing a pulse occurring at a time after the start of each transition in said incoming waveform and before a period T after the start of each transition in said incoming waveform.

Claim 12

The circuit in accordance with claim 10 wherein said first detecting means includes a first logical exclusive OR gate and said second detecting means includes a second logical exclusive OR gate, the first logical exclusive OR gate receiving its inputs from the incoming waveform and the first one of said set of delayed versions of said incoming waveform, the second logical exclusive OR gate receiving its inputs from the second and the third of said set of delayed versions of said incoming waveform.

Claim 13

The circuit in accordance with claim 11 wherein: said third detecting means includes a third logical exclusive OR gate, said third logical exclusive OR gate receiving its inputs from said incoming waveform and the second of said set of delayed versions of said incoming waveform; and said initializing means includes a third logical NAND gate, said third logical NAND gate receiving its inputs from the output of said third exclusive OR gate and an output of said isolating means.

Claim 14

The circuit in accordance with claim 12 wherein the first, second and third ones of said set of delayed versions of said incoming waveform correspond to the incoming waveform delayed by 1/4 T, 1/2 T and 3/4 T, respectively.

Claim 15

The circuit in accordance with claim 10 wherein said isolating means includes: composite clock forming means, connected to the output of said first and said second detecting means, said composite clock forming means for forming a composite clock having two unidirectional going transitions per bit cell; toggling means, receiving an input from the output of said composite clock forming means, said toggling means including means for generating a first output which toggles between a high and low state in response to each of said unidirectional going transitions provided at said input; and first timing means, connected to the first output of said toggling means and said first detecting means, said first timing means for generating a first timing signal coincident with the start of each of said guaranteed transitions in said incoming waveform.

Claim 16

The circuit in accordance with claim 14 wherein said toggling means further includes a second output, said second output providing an output signal which is the inverse of said toggling means' first output.

Claim 17

The circuit in accordance with claim 15 wherein said isolating means further includes second timing means connected to the second output of said toggling means and said second detecting means, said second timing means for generating a second timing signal commencing 1/2 T after the start of each of said guaranteed transitions in said input waveform.

Claim 18

The circuit in accordance with claim 14 wherein the two unidirectional transitions per bit cell formed at the output of said composite clock forming means are spaced substantially 1/2 T apart.

Claim 19

The circuit in accordance with claim 14 wherein said composite clock forming means includes a logical NOR gate connected to the outputs of said first and said second detecting means.

Claim 20

The circuit in accordance with claim 14 wherein said toggling means includes a logical flip-flop, said logical flip-flop responsive to each of said unidirectional going transitions.

Claim 21

The circuit in accordance with claim 14 wherein said first timing signal generation means includes a first logical NAND gate, said first logical NAND gate receiving its inputs from the first output of said toggling means and the output of said first detecting means.

Claim 22

The circuit in accordance with claim 16 wherein said second timing means includes a second logical NAND gate, said second logical NAND gate receiving its inputs from the second output of said toggling means and the output of said second detecting means.

Claim 23

The circuit in accordance with claim 14 or 16 wherein said first detecting means includes a first logical exclusive OR gate and said second detecting means includes a second logical exclusive OR gate, said first exclusive OR gate receiving its inputs from the incoming waveform and the first of said set of delayed versions of said incoming waveform, said second exclusive OR gate receiving its inputs from the second and the third of said set of delayed versions of said incoming waveform.

Claim 24

The circuit in accordance with claim 15 wherein the first, second and third of said set of delayed versions of said incoming waveform correspond to the incoming waveform delayed by 1/4 T, 1/2 T and 3/4 T, respectively.

Claim 25

The circuit in accordance with claim 22 wherein: said composite clock forming means includes a logical NOR gate receiving its inputs from the output of said first and said second exclusive OR gates; said toggling means includes a logical flip-flop receiving its clocking input from the output of said NOR gate; and said first timing signal generating means includes a logical NAND gate receiving its inputs from the output of said first exclusive OR gate and the true output of said flip-flop.

Claim 26

The circuit in accordance with claim 14, 15, 17, 18, 19, 20, 21, or 23 wherein: said third detecting means includes a third logical exclusive OR gate, said third exclusive OR gate receiving its inputs from said incoming waveform and the second of said set of delayed versions of said incoming waveform; and said initializing means includes a third logical NAND gate, said third NAND gate receiving its inputs from the output of said third exclusive OR gate and an output of said toggling means.

Claim 27

The circuit in accordance with claim 22 wherein: said third detecting means includes a third logical exclusive OR gate, said third exclusive OR gate receiving its inputs from said incoming waveform and the second of said set of delayed versions of said incoming waveform; and said initializng means includes a third logical NAND gate, said third NAND gate receiving its inputs from the output of said third exclusive OR gate and an output of said toggling means.

Claim 28

The circuit in accordance with claim 24 wherein: said third detecting means includes a third logical exclusive OR gate, said third exclusive OR gate receiving its inputs from said incoming waveform and the second of said set of delayed versions of said incoming waveform; and said initializing means includes a third logical NAND gate, said third NAND gate receiving its inputs from the output of said third exclusive OR gate and an output of said toggling means.

Claim 29

The circuit in accordance with claim 27 wherein said logical flip-flop is a D-type flip-flop, the D input to the said flip-flop connected to the output of said third NAND gate, the true output of said flip-flop providing one of the inputs to said third NAND gate.

Claim 30

The circuit in accordance with claim 5 wherein said first, second and third ones of said set of delayed versions of said incoming waveform correspond to the incoming waveform delayed by 1/4 T, 1/2 T and 3/4 T, respectively.

Claim 31

A self-synchronizing circuit for reconstructing the timing information encoded in an incoming double frequency transition-event waveform, said incoming waveform characterized as including both guaranteed and non-guaranteed transitions, said incoming waveform further characterized as having a bit cell duration of T, said circuit arrangement comprising: delay line means, responsive to said incoming waveform, said delay line means for generating a set of delayed versions of said incoming waveform; detecting means, responsive to said incoming waveform and said set of delayed versions of said incoming waveform, said detecting means for detecting each transition in said incoming waveform and producing first and second transition waveforms, each of said transition waveforms identifying each transition in said incoming waveform; isolating means, connected to said detecting means, said isolating means for isolating out the set of guaranteed transitions in said detected transitions, said isolating means including a logical NOR gate responsive to said detecting means, a logical flip-flop responsive to said logical NOR gate, and a first logical NAND gate responsive to said detecting means and said flip-flop; and synchronizing means, connected to said delay line means and said isolating means and responsive to said incoming waveform, said synchronizing means for assuring that said isolating means is properly synchronized with said incoming waveform.

Claim 32

A self-synchronizing circuit for reconstructing the timing information encoded in an incoming double frequency transition-event waveform, said incoming waveform characterized as including both guaranteed and non-guaranteed transitions, said incoming waveform further characterized as having a bit cell duration of T, said circuit arrangement comprising: delay line means, responsive to said incoming waveform, said delay line means for generating a set of delayed versions of said incoming waveform; detecting means, responsive to said incoming waveform and said set of delayed versions of said incoming waveform, said detecting means for detecting each transition in said incoming waveform and producing first and second transition waveforms, each of said transition waveforms identifying each transition in said incoming waveform; isolating means, connected to said detecting means, said isolating means for isolating out the set of guaranteed transitions in said detected transitions, said isolating means including a logical NOR gate responsive to said detecting means, a logical flip-flop responsive to said logical NOR gate, and a first logical NAND gate responsive to said detecting means and said flip-flop; and synchronizing means, connected to said delay line means and said isolating means and responsive to said incoming waveform, said synchronizing means for assuring that said isolating means is properly synchronized with said incoming waveform.

Claim 33

The circuit in accordance with claim 30 wherein said detecting means includes: a first logical exclusive OR gate receiving its inputs from said incoming waveform and a first one of said set of delayed versions of said incoming waveform; and a second logical exclusive OR gate receiving its inputs from a second one and a third one of said set of delayed versions of said incoming waveform.

Claim 34

The circuit in accordance with claim 31 wherein said synchronizing means includes: a third logical exclusive OR gate receiving its inputs from said incoming waveform and said second one of said set of delayed versions of said incoming waveform; and a third logical NAND gate receiving its inputs from the output of said third exclusive OR gate and an output of said isolating means, the output of said third NAND gate providing an input to said isolating means.

Claim 35

The circuit arrangement in accordance with claim 32 wherein: said logical NOR gate receives its inputs from the outputs of said first and said second exclusive OR gates; said logical flip-flop receives its clocking input from the output of said logical OR gate; and said first logical NAND gate receives its inputs from the output of said first exclusive OR gate and the true output of said flip-flop, whereby a first set of timing information is reconstructed at the output of said first NAND gate.

Claim 36

The circuit arrangement in accordance with claim 33 wherein said first, second and third ones of said delayed versions of said incoming waveform correspond to the incoming waveform delayed by 1/4 T, 1/2 T and 3/4 T, respectively.

Claim 37

A self-synchronizing circuit for reconstructing the timing information encoded in an incoming double frequency transition-event waveform, said incoming waveform characterized as including both guaranteed and non-guaranteed transitions, said incoming waveform further characterized as having a bit cell duration of T, said circuit arrangement comprising: delay line means, responsive to said incoming waveform, said delay line means for generating a set of delayed versions of said incoming waveform; detecting means, responsive to said incoming waveform and said set of delayed versions of said incoming waveform, said detecting means for detecting each transition in said incoming waveform and producing first and second transition waveforms, each of said transition waveforms identifying each transition in said incoming waveform, the second transition waveform corresponding to the first transition waveform delayed by a fixed time interval; composite clock forming means, connected to said detecting means, said composite clock forming means for forming a composite clock from said two transition waveforms; toggling means, receiving an input from the output of said composite clock forming means, said toggling means including means for generating a first output which toggles between a high and low state in response to each one of a set of unidirectional going transitions in said composite clock; first timing means, connected to the first output of said toggling means and said detecting means, said first timing means for generating a first timing signal coincident with the start of each of said guaranteed transitions in said incoming waveform; and synchronizing means, connected to said delay line means and said toggling means and responsive to said incoming waveform, said synchronizing means for assuring that said toggling means is properly synchronized with said incoming waveform.

Claim 38

A self-synchronizing circuit for reconstructing the timing information encoded in an incoming double frequency transition-event waveform, said incoming waveform characterized as including both guaranteed and non-guaranteed transitions, said incoming waveform further characterized as having a bit cell duration of T, said circuit arrangement comprising: delay line means, responsive to said incoming waveform, said delay line means for generating a set of delayed versions of said incoming waveform; detecting means, responsive to said incoming waveform and said set of delayed versions of said incoming waveform, said detecting means for detecting each transition in said incoming waveform and producing first and second transition waveforms, each of said transition waveforms identifying each transition in said incoming waveform, the second transition waveform corresponding to the first transition waveform delayed by a fixed time interval; composite clock forming means, connected to said detecting means, said composite clock forming means for forming a composite clock from said two transition waveforms; toggling means, receiving an input from the output of said composite clock forming means, said toggling means including means for generating a first output which toggles between a high and low state in response to each one of a set of unidirectional going transitions in said composite clock; first timing means, connected to the first output of said toggling means and said detecting means, said first timing means for generating a first timing signal coincident with the start of each of said guaranteed transitions in said incoming waveform; and synchronizing means, connected to said delay line means and said toggling means and responsive to said incoming waveform, said synchronizing means for assuring that said toggling means is properly synchronized with said incoming waveform.

Claim 39

The circuit in accordance with claim 35 wherein said synchronizing means includes: third detecting means, responsive to said incoming waveform and a second one of said set of delayed versions of said incoming waveform, said third detecting means for comparing said incoming waveform with said second delayed version of said incoming waveform; and initializing means, connected to said third detecting means and responsive to said toggling means, said initializing means for initializing said toggling means to isolate the next received guaranteed transition in said incoming waveform.

Claim 40

The circuit in accordance with claim 36 wherein said detecting means includes: first detecting means, responsive to said incoming waveform and a first one of said set of delayed versions of said incoming waveform, said first detecting means for generating said first transition waveform, said first transition waveform providing a pulse coincident with the start of each transition in said incoming waveform; and second detecting means, responsive to the second and a third of said set of delayed versions of said incoming waveform, said second detecting means for generating said second transition waveform, said second transition waveform corresponding to the first transition waveform delayed by a fixed time interval, the second transition waveform providing a pulse occurring at a time after the start of each transition in said incoming waveform and before a period T after the start of each transition in said incoming waveform.

Claim 41

The circuit in accordance with claim 37 wherein said first detecting means includes a first logical exclusive OR gate and said second detecting means includes a second logical exclusive OR gate, the first logical exclusive OR gate receiving its inputs from the incoming waveform and the first one of said set of delayed versions of said incoming waveform, the second logical exclusive OR gate receiving its inputs from the second and the third of said set of delayed versions of said incoming waveform.

Claim 42

The circuit in accordance with claim 38 wherein: said third detecting means includes a third logical exclusive OR gate, said third logical exclusive OR gate receiving its inputs from said incoming waveform and the second of said set of delayed versions of said incoming waveform; and said initializing means includes a third logical NAND gate, said third logical NAND gate receiving its inputs from the output of said third exclusive OR gate and an output of said isolating means.

Claim 43

The circuit in accordance with claim 39 wherein: said composite clock forming means includes a logical NOR gate receiving its inputs from the output of said first and said second exclusive OR gates; said toggling means includes a logical flip-flop receiving its clocking input from the output of said NOR gate; and said first timing means includes a logical NAND gate receiving its inputs from the output of said first exclusive OR gate and the true output of said flip-flop.

Claim 44

The circuit in accordance with claim 40 wherein: said third detecting means includes a third logical exclusive OR gate, said third exclusive OR gate receiving its inputs from said incoming waveform and the second of said set of delayed versions of said incoming waveform; and said initializing means includes a third logical NAND gate, said third NAND gate receiving its inputs from the output of said third exclusive OR gate and an output of said isolating means.

Claim 45

A self-synchronizing circuit for reconstructing the timing information encoded in an incoming double frequency transition-event waveform, said incoming waveform characterized as including both guaranteed and non-guaranteed transitions, said incoming waveform further characterized as having a bit cell duration of T, said circuit arrangement comprising: delay line means, responsive to said incoming waveform, said delay line means for generating a set of delayed versions of said incoming waveform; detecting means, responsive to said incoming waveform and said set of delayed versions of said incoming waveform, said detecting means for detecting each transition in said incoming waveform and producing first and second transition waveforms, each of said transition waveforms identifying each transition in said incoming waveform; isolating means, connected to said detecting means, said isolating means for isolating out the set of guaranteed transitions in said detected transitions, said isolating means including a first logical NAND gate responsive to said detecting means to produce at the output of said first logical NAND gate a first set of timing information; and synchronizing means, connected to said delay line means and said isolating means and responsive to said incoming waveform, said synchronizing means for assuring that said isolating means is properly synchronized with said incoming waveform.

Claim 46

A self-synchronizing circuit for reconstructing the timing information encoded in an incoming double frequency transition-event waveform, said incoming waveform characterized as including both guaranteed and non-guaranteed transitions, said incoming waveform further characterized as having a bit cell duration of T, said circuit arrangement comprising: delay line means, responsive to said incoming waveform, said delay line means for generating a set of delayed versions of said incoming waveform; detecting means, responsive to said incoming waveform and said set of delayed versions of said incoming waveform, said detecting means for detecting each transition in said incoming waveform and producing first and second transition waveforms, each of said transition waveforms identifying each transition in said incoming waveform; isolating means, connected to said detecting means, said isolating means for isolating out the set of guaranteed transitions in said detected transitions, said isolating means including a first logical NAND gate responsive to said detecting means to produce at the output of said first logical NAND gate a first set of timing information; and synchronizing means, connected to said delay line means and said isolating means and responsive to said incoming waveform, said synchronizing means for assuring that said isolating means is properly synchronized with said incoming waveform.

Claim 47

The circuit arrangement in accordance with claim 42 wherein said first logical NAND gate receives one of its inputs from an output of said detecting means.

Claim 48

The circuit arrangement in accordance with claim 43 wherein said first set of timing information identifies the commencement of each guaranteed transition in said incoming waveform.

Claim 49

The circuit arrangement in accordance with claim 42 wherein said isolating means further includes: a logical NOR gate receiving its inputs from the outputs of said detecting means; and a logical flip-flop receiving its clocking input from the output of said logical NOR gate.

Claim 50

The circuit arrangement in accordance with claim 45 wherein said detecting means includes: a first logical exclusive OR gate receiving its inputs from said incoming waveform and a first one of said delayed versions of said incoming waveform; and a second logical exclusive OR gate receiving its inputs from a second and a third delayed version of said incoming waveform.

Claim 51

The circuit arrangement in accordance with claim 46 wherein said first logical NAND gate receives its inputs from said first logical exclusive OR gate and said logical flip-flop.