US4185273A
Expired / Lapsed
US
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Data rate adaptive control device for Manchester code decoders
Assignee: United States Department of the Navy
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Filing: 1977-07-27
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Granted: 1980-01-22
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Expires: 1997-07-27
Abstract
Abstract An automatic means for decoding a wide data range of Manchester code data. Variable delay means are provided for the Manchester code decoder which are digitally controlled in response to the output of a data rate sensing circuit that provides a digital equivalent of the sensed data rate. The digital equivalent of the sensed data rate is used to optimize the amount of delay in the Manchester code decoder for the particular data rate of the data being received.
Inventors
- 👤 Richard L. Gowan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:12
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; H04L7/00; H04L7/0054; H04L7/0066; H04L7/04; H04L7/041; H04L7/046
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
366 words
A data rate adaptive control device for Manchester code decoder comprising: input means for receiving Manchester encoded data, said encoded data having a preamble which is a series of pulses, whose widths are equal and known for a particular data rate; pulse width to digital converter means connected to said input means for providing an output signal indicative of the data rate in response to the detected pulse widths of said preamble, said pulse width to digital converter means including; first and second flip-flop circuits, each of said flip-flop circuits having a j input, a k input, a clock input, a q output, and a q output; a sample rate generator having first and second outputs, the first output of said sample rate generator being connected to the j input of said first and second flip-flop circuit, the second output of said sample rate generator being connected to the k input of said first flip-flop circuit; the clock inputs of said first and second flip-flop circuits being connected to said input means for receiving said Manchester encoded data; data present sensor circuit means having an input connected to said input means for receiving said Manchester encoded data and first and second outputs; a data present flip-flop circuit means having a j input connected to the first output of said data present sensor circuit means, a reset input connected to the second output of said data present sensor circuit means, a clock input, a q output, and a q output; an AND gate having a first input connected to said input means for receiving said Manchester encoded data, a second input connected to the q output of said second flip-flop circuit, a third input connected to the q output of said first flip-flop circuit, and a fourth input connected to the q output of said data present flip-flop circuit means, for providing a single pulse of the incoming data stream to be gated out during each cycle of said sample rate generator; circuit means connected to said input means and to said pulse width to digital converter means for controlling the amount of delay of the received encoded data to provide optimum decoding of the encoded data.
Claim 2
Dependent Claim
366 words
A data rate adaptive control device for Manchester code decoder comprising: input means for receiving Manchester encoded data, said encoded data having a preamble which is a series of pulses, whose widths are equal and known for a particular data rate; pulse width to digital converter means connected to said input means for providing an output signal indicative of the data rate in response to the detected pulse widths of said preamble, said pulse width to digital converter means including; first and second flip-flop circuits, each of said flip-flop circuits having a j input, a k input, a clock input, a q output, and a q output; a sample rate generator having first and second outputs, the first output of said sample rate generator being connected to the j input of said first and second flip-flop circuit, the second output of said sample rate generator being connected to the k input of said first flip-flop circuit; the clock inputs of said first and second flip-flop circuits being connected to said input means for receiving said Manchester encoded data; data present sensor circuit means having an input connected to said input means for receiving said Manchester encoded data and first and second outputs; a data present flip-flop circuit means having a j input connected to the first output of said data present sensor circuit means, a reset input connected to the second output of said data present sensor circuit means, a clock input, a q output, and a q output; an AND gate having a first input connected to said input means for receiving said Manchester encoded data, a second input connected to the q output of said second flip-flop circuit, a third input connected to the q output of said first flip-flop circuit, and a fourth input connected to the q output of said data present flip-flop circuit means, for providing a single pulse of the incoming data stream to be gated out during each cycle of said sample rate generator; circuit means connected to said input means and to said pulse width to digital converter means for controlling the amount of delay of the received encoded data to provide optimum decoding of the encoded data.
Claim 3
Dependent Claim
35 words
The control device of claim 1 wherein a read-only memory is coupled to the output of said pulse width to digital converter for generating an output digital word in response to the sensed pulse width.
Claim 4
Dependent Claim
45 words
The control device of claim 2 wherein said circuit means includes a tapped delay line connected to said input means and to said read-only memory for providing a range of delays, one of which will be selected by the digital output from said read-only memory.
Claim 5
Dependent Claim
59 words
The control device of claim 3 wherein said circuit means further includes a plurality of logic gates connected to said delay line and to said read-only memory for gating the data signal received at said input means through a portion of said delay line corresponding to the desired delay represented by the digital output word from said read-only memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-21 | 1983-07-23 | 1984-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-21 | 1987-07-23 | 1988-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-21 | 1991-07-23 | 1992-01-22 | $7700.00 | Window Closed / Lapsed |