US4234897A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DC Free encoding for data transmission
Assignee: Ampex Corp
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Filing: 1978-10-05
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Granted: 1980-11-18
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Expires: 1998-10-05
Abstract
Abstract A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's, are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed. The onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission is detected by counting first bit states and producing a first indicating signal when the count is of parity indicating such sequence, and in response to the first indicating signal, a current bit and an adjacent bit the transmission of signal transitions is modified from the onset of such sequence to eliminate any DC component. Preferably, the possibly troublesome sequences are encoded by encoding pairs of second bit states by a single transition early in the first bit cell of the pair.
Inventors
- 👤 Jerry W. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:28
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
233 words
In a self-clocking transmission system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, second indicating means responsive to bit states for producing a second indicating signal indicating whether the number of second bit states occurring in such sequence prior to a current bit is odd or even, and transition modifying means responsive to said first and second indicating signals and to the current bit and the next succeeding bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component.
Claim 2
Dependent Claim
233 words
In a self-clocking transmission system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, second indicating means responsive to bit states for producing a second indicating signal indicating whether the number of second bit states occurring in such sequence prior to a current bit is odd or even, and transition modifying means responsive to said first and second indicating signals and to the current bit and the next succeeding bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component.
Claim 3
Dependent Claim
63 words
Apparatus in accordance with claim 1 wherein said transition modifying means modifies the transmission of signal transitions to provide a single transition corresponding to each pair of second bit states of such sequence where the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 4
Dependent Claim
170 words
Apparatus in accordance with either one of claims 2 and 3 further including decoding means responsive to transmitted signal transitions for indicating the bit states of the binary data transmitted, said decoding means comprising synchronizing means responsive to transmitted signal transitions for providing timing signals identifying bit cell intervals, detection means responsive to said transmitted signal transitions and said timing signals by producing transition identifying signals identifying received signal transitions as relatively early or relatively late in respective bit cells, and bit state recognition means responsive to said transition identifying signals by indicating a bit cell as being in the second bit state under any of the conditions of (a) a relatively late transition for the respective cell, (b) a relatively early transition for the respective cell where there is no transition for the next succeeding cell, and (c) no transition for the respective cell where there was no relatively late transition for the next preceding cell, and by indicating all other cells as being in the first bit state.
Claim 5
Dependent Claim
197 words
A self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively late in the next preceding bit cell is normally suppressed, said method comprising detecting the onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission by counting the number of first bit states and producing a first indicating signal when the number of first bit states is of predetermined parity indicating such sequence, in response to bit states indicating whether the number of second bit states in such sequence prior to a current bit is odd or even by producing a second indicating signal indicative thereof, and in response to said first and second indicating signals and to the current bit and the next succeeding bit modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component.
Claim 6
Dependent Claim
197 words
A self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively late in the next preceding bit cell is normally suppressed, said method comprising detecting the onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission by counting the number of first bit states and producing a first indicating signal when the number of first bit states is of predetermined parity indicating such sequence, in response to bit states indicating whether the number of second bit states in such sequence prior to a current bit is odd or even by producing a second indicating signal indicative thereof, and in response to said first and second indicating signals and to the current bit and the next succeeding bit modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component.
Claim 7
Dependent Claim
59 words
A method according to claim 4 wherein transmission of signal transitions is modified to produce a single transition corresponding to each pair of second bit states of such sequence when the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 8
Independent Claim
131 words
A method according to either one of claims 4 and 5 wherein the transmitted signal is decoded by deriving timing signals from the transmitted data signal transitions for identifying bit cell intervals, producing transition identifying signals identifying received signal transitions as relatively early or relatively late in respective bit cells, and from said transition identifying signals indicating a bit cell as in the second bit state under any of the conditions of (a) a relatively late transition for the respective cell, (b) a relatively early transition for the respective cell where there is no transition for the next succeeding cell, and (c) no transition for the respective cell where there was no relatively late transition for the next preceding cell, all other cells being indicated as in the first bit state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-18 | 1984-05-19 | 1984-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-18 | 1988-05-19 | 1988-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-18 | 1992-05-19 | 1992-11-18 | $7700.00 | Window Closed / Lapsed |