US4242755A
Expired / Lapsed
US
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Circuit arrangement for decoding digital signals
Assignee: Thales SA
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Filing: 1979-09-18
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Granted: 1980-12-30
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Expires: 1999-09-18
Abstract
Abstract A demodulator for binary messages of the diphase type comprises a sampling circuit controlled by a local clock whose cycle is approximately 1/n th of the bit length of the incoming signals (with n=8 in a specific instance), this circuit deriving (n-2) samples from each message bit which are then analyzed in a programmed memory to determine whether the bit being sampled has one of six acceptable configurations, namely a bit of logical value "0" or "1" in either a normal, a leading or a lagging position with reference to a decoding interval T equaling n clock cycles. If a different configuration is detected, an error signal is generated. The decoding interval is measured by a counter, stepped by the local clock, which is adjusted by recalibrating commands from the programmed memory to shorten or lengthen the next decoding interval when a bit is found to lead or lag by a full clock cycle, thereby restoring the normal relative time position of the message bits and the decoding interval. A validation signal emitted by the bit analyzer in the presence of an acceptable configuration enables the generation of a synchronization pulse at a predetermined time in the decoding interval to mark the instant at which the received message bit can be correctly read either in a reconstituted bit sequence or in the original binary pulse train delayed by one interval T of n clock cycles.
Inventors
- 👤 Pierre Gauzan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:53
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/068
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
255 words
A demodulator for binary message signals with bits distinguished by a characteristic phasing of two voltage levels, comprising: local timing means for establishing a train of clock pulses with a cycle T1; signal-generating means controlled by said clock pulses to establish a decoding interval T normally equaling n clock cycles T1 where n is an integer equal to at least 3; sampling means connected to receive incoming message signals with bits whose length T' approximately equals said decoding interval T and to derive a plurality of samples from each of said bits; bit-analyzing means connected to said sampling means for receiving therefrom at least some of the samples of an incoming message bit during each decoding interval in response to a transfer command from said signal-generating means, said bit-analyzing means being programmed to distinguish between predetermined acceptable configurations of bit samples and nonacceptable configurations differing therefrom and to discriminate among centered and off-centered acceptable configurations, with emission of a validating signal in the presence of any acceptable configuration and of a recalibration command in the presence of an off-centered configuration, said signal-generating means being responsive to said recalibrating command for altering the next decoding interval by one clock cycle T1 to re-establish a normal time position between said decoding interval and the following message bits; and circuit means connected to said bit-analyzing means for receiving said validating signal therefrom and controlled by said signal-generating means for emitting a synchronizing pulse, in the presence of said validating signal, at a predetermined time in each decoding interval.
Claim 2
Dependent Claim
255 words
A demodulator for binary message signals with bits distinguished by a characteristic phasing of two voltage levels, comprising: local timing means for establishing a train of clock pulses with a cycle T1; signal-generating means controlled by said clock pulses to establish a decoding interval T normally equaling n clock cycles T1 where n is an integer equal to at least 3; sampling means connected to receive incoming message signals with bits whose length T' approximately equals said decoding interval T and to derive a plurality of samples from each of said bits; bit-analyzing means connected to said sampling means for receiving therefrom at least some of the samples of an incoming message bit during each decoding interval in response to a transfer command from said signal-generating means, said bit-analyzing means being programmed to distinguish between predetermined acceptable configurations of bit samples and nonacceptable configurations differing therefrom and to discriminate among centered and off-centered acceptable configurations, with emission of a validating signal in the presence of any acceptable configuration and of a recalibration command in the presence of an off-centered configuration, said signal-generating means being responsive to said recalibrating command for altering the next decoding interval by one clock cycle T1 to re-establish a normal time position between said decoding interval and the following message bits; and circuit means connected to said bit-analyzing means for receiving said validating signal therefrom and controlled by said signal-generating means for emitting a synchronizing pulse, in the presence of said validating signal, at a predetermined time in each decoding interval.
Claim 3
Dependent Claim
71 words
A demodulator as defined in claim 1 wherein said signal-generating means comprises a clock-pulse counter receptive to a first recalibrating command for shortening the next decoding interval to (n-1) clock cycles in the event of a leading time position of said bit samples and to a second recalibrating command for lengthening the next decoding interval to (n+1) clock cycles in the event of a lagging time position of said bit samples.
Claim 4
Dependent Claim
28 words
A demodulator as defined in claim 2 wherein said clock-pulse counter has loading inputs connected to receive said first and second recalibration commands for establishing different initial counts.
Claim 5
Dependent Claim
61 words
A demodulator as defined in claim 1, 2 or 3 wherein said sampling means comprises an n-stage shift register and a buffer memory connected to receive from said shift register the voltage levels stored in the stages thereof with the exception of at least the first and the last voltage level sampled during a normal decoding interval of n clock cycles.
Claim 6
Dependent Claim
54 words
A demodulator as defined in claim 4 wherein said bit-analyzing means comprises a programmed memory connected to said buffer memory and a decoding circuit connected to said programmed memory for producing said validating signal in the presence of an acceptable configuration and for emitting an error signal in the presence of an unacceptable configuration.
Claim 7
Dependent Claim
31 words
A demodulator as defined in claim 5 wherein said decoding circuit is provided with two outputs carrying respective bit-identifying pulses in the presence of acceptable configurations corresponding to different voltage levels.
Claim 8
Dependent Claim
25 words
A demodulator as defined in claim 6, further comprising logical circuitry connected to said outputs for reconstituting said incoming message signals from said bit-identifying pulses.
Claim 9
Dependent Claim
29 words
A demodulator as defined in claim 6, further comprising logical circuitry connected to said outputs for generating said validating signal in the presence of either of said bit-identifying pulses.
Claim 10
Dependent Claim
77 words
A demodulator as defined in claim 5, further comprising logical circuitry connected to said decoding circuit for generating a recognition pulse upon detecting a predetermined grouping of bit samples constituting a synchronization code in an initial phase of message reception, said grouping including at least one special configuration acceptable only during said initial phase, said programmed memory being responsive to said recognition pulse for making said special configuration unacceptable for the remaining duration of an incoming message.
Claim 11
Dependent Claim
49 words
A demodulator as defined in claim 9, further comprising conversion means connected to receive said incoming message signals for deriving therefrom a duration signal terminating at the end of said message, said logical circuitry being responsive to said duration signal for detecting said grouping only in said initial phase.
Claim 12
Dependent Claim
49 words
A demodulator as defined in claim 4, further comprising logical circuitry forming an (n+1) th stage for said shift register for emitting, under the control of said signal-generating means, a sequence of incoming bits delayed by n clock cycles in a predetermined time position relative to said synchronizing pulse.
Claim 13
Dependent Claim
42 words
In combination, a transmitter generating a diphase-coded binary message and a receiver including a demodulator as defined in claim 1, 2 or 3 linked with said transmitter by a two-wire line, said transmitter comprising a bit timer independent of said signal-generating means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-30 | 1984-06-30 | 1984-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-30 | 1988-06-30 | 1988-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-30 | 1992-06-30 | 1992-12-30 | $7700.00 | Window Closed / Lapsed |