US4035601A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrical circuit arrangements responsive to serial digital signals forming multi-byte data-words
Assignee: GEC-PLESSEY CRYPTO Ltd
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Filing: 1975-06-17
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Granted: 1977-07-12
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Expires: 1995-06-17
Abstract
Abstract Envisages the use of a format of serial digital signalling in which each data word comprises a predetermined number of bytes formed by bits of substantially uniform duration and in which each byte comprises a "start" bit of a first binary significance (e.g. 0) a "stop" bit having a second binary significance (e.g. 1) and an identical plurality of "data" bits immediately succeeding said "start" bit and in which the final byte of the data-word is characterized in that it has an additional bit having said first binary significance 0 interposed between last "data" bit and the "stop" bit thereof. The reading of that bit immediately succeeding the last "data" bit of each byte of each data-word of a transmission produce a so-called synchronizing pulse-sequence comprising bits of said second significance for all bytes except that last and a bit of said first significance for the last byte.
Inventors
- 👤 Charles Allan Isaacs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:29
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/0078; H04L7/00; H04L7/04; H04L7/041; H04L7/044
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
209 words
In or for use in a digital-data transmission system, a signalling response circuit for incoming signals having a signalling format of the kind referred to and characterised in that it includes (i) register means for the storing of the data content of each byte of a received data-word, (ii) control logic means for producing, preparatory to reception of each byte of the data-word, either a first condition indicating that the byte currently expected is other than the last byte of a data-word or a second condition indicating that the byte expected is the last byte of a data-word and producing control signals connected to said register means, (iii) detector means for extracting from said incoming signals, pulses having time appearances appropriate to a synchronising-pulse sequence, (iv) a comparison device operative under control of each aforesaid extracted pulse and the prevailing said first or second condition to assess the presence or absence of a synchronisation error in relation to any currently received byte of a data-word and to produce a first or second output signal appropriate to said presence and absence respectively, said output signal being applied to said control logic means to cause said control logic means to produce either said first or second condition and said control signals.
Claim 2
Dependent Claim
209 words
In or for use in a digital-data transmission system, a signalling response circuit for incoming signals having a signalling format of the kind referred to and characterised in that it includes (i) register means for the storing of the data content of each byte of a received data-word, (ii) control logic means for producing, preparatory to reception of each byte of the data-word, either a first condition indicating that the byte currently expected is other than the last byte of a data-word or a second condition indicating that the byte expected is the last byte of a data-word and producing control signals connected to said register means, (iii) detector means for extracting from said incoming signals, pulses having time appearances appropriate to a synchronising-pulse sequence, (iv) a comparison device operative under control of each aforesaid extracted pulse and the prevailing said first or second condition to assess the presence or absence of a synchronisation error in relation to any currently received byte of a data-word and to produce a first or second output signal appropriate to said presence and absence respectively, said output signal being applied to said control logic means to cause said control logic means to produce either said first or second condition and said control signals.
Claim 3
Dependent Claim
118 words
A signalling response circuit as claimed in claim 1 in which said control logic means comprises one stage for each byte of the data-word, the stages being activated on a mutually-exclusive basis under the control of said first or second output signals from said comparison device and according to which stage is set said control logic means is effective to connect a said first or a said second condition to said comparison device, and to connect one of said control signals to a particular byte-storage section of said register means; the first condition being produced when a stage other than the last stage is set whereas the second condition is produced only when the last stage is set.
Claim 4
Dependent Claim
120 words
A signalling response circuit as claimed in claim 2 in which said control logic means is controlled (a) for the cyclically setting of its stages by said first output signal generated by said comparison means each time a received synchronising pulse is in conformity with a said first or second condition applied thereto, and (b) to cause the first stage to be set, if not already so, by said second output signal generated by said comparison means in the event of a received pulse and said first or second condition not being in conformity; said second output signal causing a re-set pulse to be applied to said register means by one of said control signals from said control logic means.
Claim 5
Dependent Claim
89 words
A signalling response circuit as claimed in claim 1 in which the comparison device is operative as a result of the assessment to exercise such control upon the control logic means that upon receipt of said first output signal, said control logic means produces a one of said control signals connected to said register means for cancelling the registration of the current byte in the register means and said control logic means is caused to assume a state corresponding to the reception of the initial byte of a data-word.
References Cited (Backward Citations)
US3730998A
Cited
US3883729A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-11 | 1981-01-10 | 1981-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-11 | 1985-01-10 | 1985-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-11 | 1989-01-10 | 1989-07-12 | $7700.00 | Window Closed / Lapsed |