Time multiplex frame correlation device

Claim 2

Device for the automatic search for the characteristic data elements of a time multiplexing frame having an unknown number N of bits and at least one repetitive word comprising clock means providing clock signals at the frequency of the bits in said time multiplexing frame, a delay circuit having a variable delay of n clock signals, a correlation circuit receiving directly at a first input successive bits of successive frames and at a second input said successive bits via said delay circuit, a detection circuit means for detecting s successive coincidences between the successive bits and the delayed bits, and control means for varying the delay of said delay circuit until s successive coincidences are detected for which the number N of bits in the frame is equal to the number n of clock signals.

Claim 3

Device for the automatic search for the characteristic data elements of a time multiplexing frame having an unknown number of bits and at least one repetitive word comprising clock means providing clock signals at the frequency of the bits in said time multiplexing frame, correlation means operating in synchronism with said clock signals for comparing a first series of S bits in said frame with a second series of S bits positioned in said frame n clock signals before said first series, and control means for changing the value of n until a correlation is detected between said first and second series of S bits, wherein said correlation means comprises a delay element having an adjustable duration of n clock signals, an EXCLUSIVE OR circuit having one input receiving said data elements directly and a second input receiving said data elements via said delay element, a shift register having a capacity of S bits connected to the output of said EXCLUSIVE OR circuit, and an AND gate having inputs connected to the output of each stage of said shift register.

Claim 4

Device for the automatic search for the characteristic data elements of a time multiplexing frame having an unknown number of bits and at least one repetitive word comprising clock means providing clock signals at the frequency of the bits in said time multiplexing frame, correlation means operating in synchronism with said clock signals for comparing a first series of S bits in said frame with a second series of S bits positioned in said frame n clock signals before said first series, and control means for changing the value of n until a correlation is detected between said first and second series of S bits, wherein said correlation means comprises a delay element having an adjustable duration of n clock signals, an EXCLUSIVE OR circuit having one input receiving said data elements directly and a second input receiving said data elements via said delay element, a shift register having a capacity of S bits connected to the output of said EXCLUSIVE OR circuit, and an AND gate having inputs connected to the output of each stage of said shift register.

Claim 5

Device as defined in claim 2 wherein said delay element comprises a second shift register having a plurality of stages and logic circuit means including a main counter responsive to the output of said control means for selectively short-circuiting stages of said second shift register to adjust the length thereof.

Claim 6

Device as defined in claim 3 wherein said control means includes a divider having a variable order n receiving clock signals from said clock means and inhibit means for diverting application of said clock signals from said divider until an output is provided at said AND gate.

Claim 7

Device as defined in claim 4 wherein said control means further includes a reverse counter preset to the value n, connection means connected to said inhibit means for applying to said reverse counter the clock signals diverted from said divider, and gating means for advancing said main counter during each pass of said reverse counter through zero.

Claim 8

Device as defined in claim 5 wherein said control means further includes a counter connected to count the output of said divider and is connected to said connection means so as to be reset by said clock signals diverted from said divider, a first decoder connected to the output of said counter for decoding a first value, and a first flip-flop connected to the output of said first decoder for enabling said gating means upon receipt of an output from said first decoder.

Claim 9

Device as defined in claim 6 wherein said control means further includes a second Decoder connected to the output of said counter for decoding a second value, and a second flip-flop responsive to the output of said second decoder for disabling said inhibit means to apply all clock signals to said divider.

Claim 10

Device as defined in claim 7 wherein said control means further includes a third shift register connected to the output of said divider and said AND gate, a second AND gate having inputs connected to the stages of said third shift register and an output connected to a second input of said second flip-flop.

Claim 11

Device as defined in claim 2, further including a fourth shift register having a capacity of S bits connected to receive said data elements, a plurality of indicators, and a transfer circuit connecting each stage of said fourth shift register to a respective indicator.

Claim 12

Device as defined in claim 4, further including means for overriding said inhibit means and manual means for selectively controlling, one by one, the clock signals applied to said divider.