Orse code type signals digital means for improving the signal to noise ratio of repetitive m

Claim 2

Signal processing means for generating a relatively noise free replica of a cyclic repetitive binary code sequence comprising threshold sensitive means for converting said code to first and second predetermined binary levels in response to elements of said code respectively exceeding or being less than a predetermined magnitude, a flip-flop circuitry having first and second complementary outputs, means for controlling said first output of said flip-flop circuitry at a predetermined clock sampling rate in accordance with the output level of said threshold sensitive means, a multi-bit binary adder including a least significant bit section and a most significant bit section, a multi-bit binary subtractor including a least significant bit section and a most significant bit section, the outputs of said binary adder section being applied to like significant bit sections of said binary subtractor, a plurality of shift registers each receiving as a serial input thereto the output from an associated one of said binary subtractor sections, the output of each of said shift registers being applied as input to respective like significant bit sections of said binary adder, means for timing said shift register and said binary adder and subtractor at said clock rate, means responsive to said first flip-flop output for adding a binary ''''one'''' to the count in said binary adder in response to the repetitive outputs from said plurality of shift registers collectively exhibiting a permutation of binary levels other than all said first binary levels and with said first flip-flop output exhibiting said first binary level, means responsive to said flip-flop second output for subtracting a binary ''''one'''' from the count in said binary subtractor in response to the respective outputs of said shift registers collectively exhibiting a permutation of binary levels other than all said second binary levels and with said second flip-flop output exhibiting said first binary level, and an oUtput signal comprising the binary signal circulating through a selected one of said plurality of shift registers.

Claim 3

Signal processing means as defined in claim 1 wherein said output signal comprises the binary signal circulating through the most significant bit one of said plurality of shift registers.

Claim 4

Signal processing means as defined in claim 2 wherein said clock rate is selected such that the output of said shift registers corresponds to the same point on said received code as that currently being sampled by flip-flop circuitry.

Claim 5

Signal processing means as defined in claim 3 wherein said clock rate effects a single sampling of successive elements of said input code during each element reception period.

Claim 6

Signal processing means as defined in claim 3 wherein said clock rate effects a multiple sampling of successive elements of said input code during each element reception period.

Claim 7

Signal processing means as defined in claim 1 wherein said means for adding comprises a NAND gate receiving the outputs of each of said shift registers, a first AND gate receiving the output of said NAND gate and said first output from said flip-flop as respective inputs thereto, the output from said first AND gate being applied to the least significant bit section of said binary adder; said means for subtracting comprising an OR gate receiving the outputs from each of said shift registers, a second AND gate receiving the output of said OR gate and said second output from said flip-flop as respective inputs thereto, and the output from said second AND gate being applied to the least significant bit section of said binary subtractor.

Claim 8

Signal processing means as defined in claim 6 wherein said clock rate is selected such that the output of said shift registers corresponds to the same point on said received code as that currently being sampled by flip-flop circuitry.

Claim 9

Signal processing means for generating a relatively noise free replica of a cyclic repetitive binary code sequence comprising threshold sensitive means for converting said code to first and second predetermined binary levels in response to elements of said code respectively exceeding or being less than a predetermined magnitude, a flip-flop circuitry having first and second complementary outputs, means for controlling said first output state of said flip-flop circuitry at a predetermined clock sampling rate in accordance with the output level of said threshold sensitive means, a multi-bit binary adder including a least significant bit section and a most significant bit section, a multi-bit binary subtractor including a least significant bit section and a most significant bit section, the outputs of said binary adder section being applied to like significant bit sections of said binary subtractor, a plurality of shift registers each receiving as a serial input thereto the output from an associated one of said binary subtractor sections, the output of each of said shift registers being applied as input to respective like significant bit sections of said binary adder, means for timing said shift register and said binary adder and subtractor at said clock rate, means responsive to said first flip-flop output for adding at the time of a current sample of said input signal one least significant bit to the count stored in said binary adder at the conclusion of a next preceding input signal sample, said means for adding being enabled by said first flip-flop output exhibiting said first binary level, means responsive to said second flip-flop output for subtracting at the time of a current sample of said input signal one least significant bit from the count stored in said binary subtractor at the conclusion of a next preceding input signal sample, said means for subtracting being enabled by said second flip-flop output exhibiting said first binary level, means for inhibiting said means for adding when the respective outputs of said shift registers collectively exhibit a permutation of all said first bInary levels, means for inhibiting said means for subtracting when the outputs of said shift registers collectively exhibit a permutation of all said second binary levels, and an output signal comprising the binary signal circulating through a selected one of said plurality of shift registers.

Claim 10

Signal processing means for generating a relatively noise free replica of a cyclic repetitive binary code sequence comprising threshold sensitive means for converting said code to first and second predetermined binary levels in response to elements of said code respectively exceeding or being less than a predetermined magnitude, a flip-flop circuitry having first and second complementary outputs, means for controlling said first output state of said flip-flop circuitry at a predetermined clock sampling rate in accordance with the output level of said threshold sensitive means, a multi-bit binary adder including a least significant bit section and a most significant bit section, a multi-bit binary subtractor including a least significant bit section and a most significant bit section, the outputs of said binary adder section being applied to like significant bit sections of said binary subtractor, a plurality of shift registers each receiving as a serial input thereto the output from an associated one of said binary subtractor sections, the output of each of said shift registers being applied as input to respective like significant bit sections of said binary adder, means for timing said shift register and said binary adder and subtractor at said clock rate, means responsive to said first flip-flop output for adding at the time of a current sample of said input signal one least significant bit to the count stored in said binary adder at the conclusion of a next preceding input signal sample, said means for adding being enabled by said first flip-flop output exhibiting said first binary level, means responsive to said second flip-flop output for subtracting at the time of a current sample of said input signal one least significant bit from the count stored in said binary subtractor at the conclusion of a next preceding input signal sample, said means for subtracting being enabled by said second flip-flop output exhibiting said first binary level, means for inhibiting said means for adding when the respective outputs of said shift registers collectively exhibit a permutation of all said first bInary levels, means for inhibiting said means for subtracting when the outputs of said shift registers collectively exhibit a permutation of all said second binary levels, and an output signal comprising the binary signal circulating through a selected one of said plurality of shift registers.

Claim 11

Signal processing means as defined in claim 8 wherein said output signal comprises the binary signal circulating through the most significant bit one of said plurality of shift registers.

Claim 12

Signal processing means for generating a relatively noise free replica of a cyclic repetitive binary code sequence comprising threshold sensitive means for converting said code to first and second predetermined binary levels in response to elements of said code respectively exceeding or being less than a predetermined magnitude, a flip-flop circuitry having first and second complementary outputs, means for controlling said first output of said flip-flop circuitry at a predetermined clock sampling rate in accordance with the output level of said threshold sensitive means, a multi-bit binary adder including a least significant bit section and a most significant bit section, a multi-bit binary subtractor including a least significant bit section and a most significant bit section, the outputs of said binary adder section being applied to like significant bit sections of said binary subtractor, a plurality of shift registers each receiving as a serial input thereto the output from an associated one of said binary subtractor sections, the output of each of said shift registers being applied as input to respective like significant bit sections of said binary adder, means for timing said shift register and said binary adder and subtractor at said clock rate, a NAND gate receiving the outputs of each of said shift registers, a first AND gate receiving the output of said NAND gate and said first output from said flip-flop as respective inputs thereto, the output from said first AND gate being applied to the least significant bit section of said binary adder; an OR gate receiving the outputs from each of said shift registers, a second AND gate receiving the output of said OR gate and said second output from said flip-flop as respective inputs thereto, the output from said second AND gate being applied to the least significant bit section of said binary subtractor, and an output signal comprising the binary signal circulating through a selected one of said plurality of shift registers.

Claim 13

Signal processing means for generating a relatively noise free replica of a cyclic repetitive binary code sequence comprising threshold sensitive means for converting said code to first and second predetermined binary levels in response to elements of said code respectively exceeding or being less than a predetermined magnitude, a flip-flop circuitry having first and second complementary outputs, means for controlling said first output of said flip-flop circuitry at a predetermined clock sampling rate in accordance with the output level of said threshold sensitive means, a multi-bit binary adder including a least significant bit section and a most significant bit section, a multi-bit binary subtractor including a least significant bit section and a most significant bit section, the outputs of said binary adder section being applied to like significant bit sections of said binary subtractor, a plurality of shift registers each receiving as a serial input thereto the output from an associated one of said binary subtractor sections, the output of each of said shift registers being applied as input to respective like significant bit sections of said binary adder, means for timing said shift register and said binary adder and subtractor at said clock rate, a NAND gate receiving the outputs of each of said shift registers, a first AND gate receiving the output of said NAND gate and said first output from said flip-flop as respective inputs thereto, the output from said first AND gate being applied to the least significant bit section of said binary adder; an OR gate receiving the outputs from each of said shift registers, a second AND gate receiving the output of said OR gate and said second output from said flip-flop as respective inputs thereto, the output from said second AND gate being applied to the least significant bit section of said binary subtractor, and an output signal comprising the binary signal circulating through a selected one of said plurality of shift registers.

Claim 14

Signal processing means as defined in claim 10 wherein said output signal comprises the binary signal circulating through the most significant bit one of said plurality of shift registers.