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Method for manufacturing a semiconductor device

Assignee: Oki Electric Industry Co Ltd
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Filing: 1988-08-24
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Granted: 1989-07-25
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Expires: 2008-08-24
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Abstract

Abstract A method for manufacturing a semicondcutor device includes, steps of forming a poly silicon layer at a predetermined area for a base electrode on a surface of a thin insulating film, forming an insulating film at a sidewall of the exposed poly silicon layer, growing first and second selective epitaxial layers on the exposed surface of a silicon substrate to connect the epitaxial layer with the poly silicon layer and forming an active base and an emitter in the epitaxial layer so that the poly silicon layer is constituted as a pull-out electrode for the base.

Inventors

  • 👤 Ken-ichi Suzuki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 13:42
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 186 words
A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first insulating film on a semiconductor substrate having a buried diffusion region; (b) forming a poly crystalline semiconductor layer on a predetermined surface of the first insulating film and subsequently covering the same with a second insulating film; (c) forming an opening penetrating through the second insulating film, the poly crystalline semiconductor layer and the first insulating film to reach a surface of the semiconductor substrate; (d) forming a third insulating film on a side wall of the poly crystalline semiconductor layer exposed by forming the opening; (e) selectively forming a first step single crystalline semiconductor layer on the exposed semiconductor substrate; (f) removing, subsequent to step e), the third insulating film to expose the sidewall of the poly crystalline semiconductor layer; (g) selectively forming a second step single crystalline semiconductor layer on the first step single crystalline semiconductor layer so as to be connected to the poly crystalline semiconductory layer; and (h) forming an active base region and an emitter region in the second step single crystalline semiconductory layer.
Claim 2
Independent Claim 186 words
A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first insulating film on a semiconductor substrate having a buried diffusion region; (b) forming a poly crystalline semiconductor layer on a predetermined surface of the first insulating film and subsequently covering the same with a second insulating film; (c) forming an opening penetrating through the second insulating film, the poly crystalline semiconductor layer and the first insulating film to reach a surface of the semiconductor substrate; (d) forming a third insulating film on a side wall of the poly crystalline semiconductor layer exposed by forming the opening; (e) selectively forming a first step single crystalline semiconductor layer on the exposed semiconductor substrate; (f) removing, subsequent to step e), the third insulating film to expose the sidewall of the poly crystalline semiconductor layer; (g) selectively forming a second step single crystalline semiconductor layer on the first step single crystalline semiconductor layer so as to be connected to the poly crystalline semiconductory layer; and (h) forming an active base region and an emitter region in the second step single crystalline semiconductory layer.
Claim 3
Independent Claim 222 words
A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first insulating film on a semiconductor substrate having a buried diffusion region; (b) forming a poly crystalline semiconductor layer on a predetermined surface of the first insulating film and subsequently covering the same with a second insulating film; (c) forming an opening penetrating through the second insulating film, the poly crystalline semiconductor layer and the first insulating film to reach a surface of the semiconductor substrate; (d) forming a third insulating film on a sidewall of the poly crystalline semiconductor layer exposed by forming the opening; (e) selectively forming a first step single crystalline semiconductor layer on the exposed semiconductor substrate; (f) removing, subsequent to step e, the third insulating film to expose the sidewall of the poly crystalline semiconductor layer; (g) selectively forming a second step single crystalline semiconductor layer on the first step single crystalline semiconductor layer so as to be connected to the poly crystalline semiconductor layer; (h) forming a fourth insulating film by means of self-alignment on a sidewall of the second insulating film so as to cover a juncture of the exposed second step single crystalline semiconductor layer and the poly crystalline semiconductor layer; and (i) forming an opening within the first mentioned opening for diffusion to form an emitter region.
Claim 4
Independent Claim 222 words
A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first insulating film on a semiconductor substrate having a buried diffusion region; (b) forming a poly crystalline semiconductor layer on a predetermined surface of the first insulating film and subsequently covering the same with a second insulating film; (c) forming an opening penetrating through the second insulating film, the poly crystalline semiconductor layer and the first insulating film to reach a surface of the semiconductor substrate; (d) forming a third insulating film on a sidewall of the poly crystalline semiconductor layer exposed by forming the opening; (e) selectively forming a first step single crystalline semiconductor layer on the exposed semiconductor substrate; (f) removing, subsequent to step e, the third insulating film to expose the sidewall of the poly crystalline semiconductor layer; (g) selectively forming a second step single crystalline semiconductor layer on the first step single crystalline semiconductor layer so as to be connected to the poly crystalline semiconductor layer; (h) forming a fourth insulating film by means of self-alignment on a sidewall of the second insulating film so as to cover a juncture of the exposed second step single crystalline semiconductor layer and the poly crystalline semiconductor layer; and (i) forming an opening within the first mentioned opening for diffusion to form an emitter region.

References Cited (Backward Citations)

US4101350A Cited
US4231819A Cited
US4669180A Cited
US4710241A Cited
JPS62160762A Cited
JPS62189753A Cited
JPS62211951A Cited
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US4745087A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-07-24 1993-01-23 1993-07-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-07-24 1997-01-23 1997-07-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-07-24 2001-01-23 2001-07-25 $7700.00 Window Closed / Lapsed

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