US4735912A
Expired / Lapsed
US
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Process of fabricating a semiconductor IC device
Assignee: Oki Electric Industry Co Ltd
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Filing: 1987-06-03
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Granted: 1988-04-05
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Expires: 2007-06-03
Abstract
Abstract In a process of fabricating a semiconductor IC device, a semiconductor substrate (1) having a first region (3) of a first conduction type which is electrically isolated is prepared, on which a polycrystalline semiconductor layer, and oxidation-resistant layers (8 1 , 8 2 ) are formed in turn. In part of the first region that is not covered by the oxidation-resistant layers, second regions (6 2 , 6 2 ) of a second conduction type are formed. Parts of the polycrystalline semiconductor layer that are not covered by the oxidation-resistant layers are selectively oxidized. After removal of the oxidation-resistant layers, an impurity of the second conduction type is introduced in the polycrystalline semiconductor layers, and is diffused therefrom into parts of the first regions beneath them to form therein a third region (10) and a fourth region (6 1 ) of the second conduction. Selected parts of the surfaces of the polycrystalline layers are exposed. An impurity of the first conduction type is introduced through the exposed surface in the polycrystalline semiconductor layer on the fourth region (6 1 ), and diffused therefrom into part of the fourth region to form therein a fifth region (11) of the first conduction type.
Inventors
- 👤 Akira Kawakatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:45
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/40; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
225 words
A process of fabricating a semiconductor IC device comprising the steps of: (a) preparing a semiconductor substrate (1) having a first region (3) of a first conduction type which is electrically isolated, (b) forming a polycrystalline semiconductor layer (7) on the semiconductor substrate, (c) forming oxidation-resistant layers (8 1 , 8 2 ) on the polycrystalline semiconductor layer, (d) forming, in part of the first region that is not covered by the oxidation-resistant layers, second regions (6 2 , 6 2 ) of a second conduction type, (e) selectively oxidizing parts of the polycrystalline semiconductor layer that are not covered by the oxidation-resistant layers, (f) removing the oxidation-resistant layers, (g) introducing an impurity of the second conduction type in the polycrystalline semiconductor layers, (h) diffusing the impurity from the polycrystalline semiconductor layers into parts of the first regions beneath the polycrystalline semiconductor layers to form therein, a third region (10) and a fourth region (6 1 ) of the second conduction type, (i) exposing selected parts of the surfaces of the polycrystalline layers, (j) introducing an impurity of the first conduction type in the polycrystalline semiconductor layer on the fourth region (6 1 ) through the exposed surface, and (k) diffusing the impurity from the polycrystalline layer into part of the fourth region to form therein a fifth region (11) of the first conduction type.
Claim 2
Dependent Claim
225 words
A process of fabricating a semiconductor IC device comprising the steps of: (a) preparing a semiconductor substrate (1) having a first region (3) of a first conduction type which is electrically isolated, (b) forming a polycrystalline semiconductor layer (7) on the semiconductor substrate, (c) forming oxidation-resistant layers (8 1 , 8 2 ) on the polycrystalline semiconductor layer, (d) forming, in part of the first region that is not covered by the oxidation-resistant layers, second regions (6 2 , 6 2 ) of a second conduction type, (e) selectively oxidizing parts of the polycrystalline semiconductor layer that are not covered by the oxidation-resistant layers, (f) removing the oxidation-resistant layers, (g) introducing an impurity of the second conduction type in the polycrystalline semiconductor layers, (h) diffusing the impurity from the polycrystalline semiconductor layers into parts of the first regions beneath the polycrystalline semiconductor layers to form therein, a third region (10) and a fourth region (6 1 ) of the second conduction type, (i) exposing selected parts of the surfaces of the polycrystalline layers, (j) introducing an impurity of the first conduction type in the polycrystalline semiconductor layer on the fourth region (6 1 ) through the exposed surface, and (k) diffusing the impurity from the polycrystalline layer into part of the fourth region to form therein a fifth region (11) of the first conduction type.
Claim 3
Dependent Claim
39 words
A process according to claim 1, further comprising the steps of thermally oxidizing the surface of the polycrystalline layer after the removal of the oxidation-resistant layers at step (f) and before the introduction of the impurity at step (g).
Claim 4
Dependent Claim
47 words
A process according to claim 1, wherein, at step (g) the impurity is introduced to a high concentration into a first part (7 1 ) of the polycrystalline semiconductor layer and to a low concentration into a second part (7 2 ) of the polycrystalline semiconductor layer.
Claim 5
Dependent Claim
72 words
A process according to claim 3, wherein the impurity is introduced by ion-implantation into the first part (7 1 ) and the second part (7 2 ) of the polycrystalline semiconductor layer, and by additional ion-implantation with a resist layer covering the second part (7 2 ) of the polycrystalline semiconductor layer, the high concentration of the impurity in the first part (7 1 ) of the polycrystalline semiconductor layer is achieved.
Claim 6
Dependent Claim
35 words
A process according to claim 1, wherein at step (d) an impurity of the second conduction type is ion-implanted through the polycrystalline semiconductor layer, with the oxidation-resistant layers acting as a mask against the ion-implantation.
Claim 7
Dependent Claim
62 words
A process according to claim 1, wherein the preparation of the semiconductor substrate at step (a) comprises (a1) forming, in a semiconductor substrate of the second conduction type, a buried layer (2) of the first conduction type and an epitaxial layer (3, 5) of the first conduction type, and (a2) forming an element isolation formed at least partially of an insulating layer.
Claim 8
Dependent Claim
48 words
A process according to claim 1, wherein the first region is divided into two regions, the second to the fifth regions are formed in one of the two regions, and a sixth region (5) of the first conduction type is formed in the other of the two regions.
Claim 9
Dependent Claim
25 words
A process according to claim 7, wherein the formation of the sixth region (5) is carried out before the formation of the polycrystalline semiconductor layer.
Claim 10
Dependent Claim
18 words
A process according to claim 1, wherein the formation of the polycrystalline semiconductor layer is implemented by deposition.
Claim 11
Dependent Claim
32 words
A process according to claim 1, wherein after exposing the surfaces of the polycrystalline layers at step (i), the polycrystalline layers are oxidized to form thin oxide layers on the polycrystalline layers.
Claim 12
Dependent Claim
50 words
A process according to claim 1, wherein the semiconductor substrate is a silicon substrate, the insulating layer is a silicon oxide layer, the polycrystalline semiconductor layer is polycrystalline silicon layer, and the oxidation-resistant layer consists of a silicon oxide film and a silicon nitride film on the silicon oxide film.
Claim 13
Dependent Claim
20 words
A process according to claim 1, wherein the first conduction type is n-type, and the second conduction type is p-type.
Claim 14
Dependent Claim
26 words
A process according to claim 12, wherein the impurity of the first conduction type is arsenic, and the impurity of the second conduction type is boron.
Claim 15
Dependent Claim
63 words
A process according to claim 1, wherein the first region is used as a collector, the fourth region is used as an active base, the fifth region is used as the emitter, the second regions are high concentration inactive-base regions, and the third region is a high concentration inactive base region connecting one of the second regions and the polycrystalline semiconductor layer thereon.
Claim 16
Dependent Claim
38 words
A process according to claim 14, wherein the polycrystalline semiconductor layer on the fifth region is used as an emitter electrode, the polycrystalline semiconductor layer on the third region is used as a lead for a base electrode.
References Cited (Backward Citations)
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