Semiconductor memory including transparent latch circuits

Claim 2

A semiconductor memory including a plurality of bit lines and a plurality of latch circuits, each of which is coupled to receive the potential of a corresponding bit line and which can operate, in response to a control signal, in a through mode, to output the potential of the corresponding bit line, or in a latch mode, to latch and then output this potential, said memory comprising: clock means for generating a cyclic clock signal; a dummy bit line; a precharge circuit for precharging the dummy bit line and said plurality of bit lines to a precharge potential during a first half of a clock cycle; a plurality of discharge means respectively provided at the intersections of a plurality of word lines and said dummy bit line, for discharging the dummy bit line during a latter half of the clock cycle when the corresponding word lines are enabled by a row decoder; and control signal generator means for generating a control signal for setting the latch circuits to the latch mode at the beginning of the first half of the clock cycle and for generating a control signal for switching the latch circuits from the latch mode to the through mode during the latter half of the clock cycle when the dummy bit line is discharged by one of the discharge means from the precharge potential to a predetermined potential.

Claim 3

The semiconductor memory according to claim 1, wherein said latch circuits are switched from the latch mode to the through mode when said control signal rises from a low level to a high level, and are switched from the through mode to the latch mode when said control signal falls from the high level to the low level.

Claim 4

The semiconductor memory according to claim 1, wherein each of said plurality of said discharge means has substantially the same structure as a memory cell of the memory.

Claim 5

The semiconductor memory according to claim 3, wherein said each of said plurality of discharge means has the same current-drive ability as that with which said memory cell discharges a bit line, and provides said dummy bit line with a capacitance which is the same as the capacitance which a memory cell imparts to a bit line.

Claim 6

The semiconductor memory according to claim 3, wherein said memory cell and each of said discharge means includes an N-type MOSFET whose source-drain path is connected between a corresponding bit line and a ground terminal, and whose gate is coupled to a corresponding word line.

Claim 7

A semiconductor memory including a plurality of bit lines and a plurality of latch circuits, each of which is coupled to receive the potential of a corresponding bit line and which can operate, in response to a control signal, in a through mode, to output the potential of the corresponding bit line, or in a latch mode, to latch and then output this potential, said memory comprising: clock means for generating a cyclic clock signal; a dummy bit line; a discharge circuit for discharging said dummy bit line and said plurality of bit lines to a discharge potential during a first half of a clock cycle; a plurality of charge means respectively provided at the intersections of a plurality of word lines and said dummy bit line, for charging said dummy bit line during a latter half of the clock cycle when the corresponding word lines are enabled by a row decoder; and control signal generator means for generating a control signal for setting the latch circuits to the latch mode at the beginning of the first half of the clock cycle and for generating a control signal for switching the latch circuits from the latch mode to the through mode during the latter half of the clock cycle when said dummy bit line is charged by one of said charge means to have a potential raised from the discharge potential to a predetermined potential.

Claim 8

A semiconductor memory including a plurality of bit lines and a plurality of latch circuits, each of which is coupled to receive the potential of a corresponding bit line and which can operate, in response to a control signal, in a through mode, to output the potential of the corresponding bit line, or in a latch mode, to latch and then output this potential, said memory comprising: clock means for generating a cyclic clock signal; a dummy bit line; a discharge circuit for discharging said dummy bit line and said plurality of bit lines to a discharge potential during a first half of a clock cycle; a plurality of charge means respectively provided at the intersections of a plurality of word lines and said dummy bit line, for charging said dummy bit line during a latter half of the clock cycle when the corresponding word lines are enabled by a row decoder; and control signal generator means for generating a control signal for setting the latch circuits to the latch mode at the beginning of the first half of the clock cycle and for generating a control signal for switching the latch circuits from the latch mode to the through mode during the latter half of the clock cycle when said dummy bit line is charged by one of said charge means to have a potential raised from the discharge potential to a predetermined potential.

Claim 9

The semiconductor memory according to claim 6, wherein memory cells for controlling the potentials of said bit lines are provided at some of the intersections of said bit lines and said word lines, and each of said charge means and each of said memory cells include a PN diode whose anode is connected to the corresponding word line, and whose cathode is connected to the corresponding bit line.

Claim 10

The semiconductor memory according to claim 6, wherein said latch circuits are switched from the latch mode to the through mode when said control signal rises from a low level to a high level, and are switched from the through mode to the latch mode when said control signal falls from the high level to the low level.

Claim 11

A synchronous semiconductor memory, comprising: a plurality of bit lines; latch circuits, each of which is ocupled to receive the potential of a corresponding bit line and which can operate, in response to a control signal rising from a low level to a high level, in a through mode to output the potential of the corresonding bit line, or, in respone to the control signal falling from the high level to the low level, in a latch mode to latch and then output this potential; clock means for generating a cyclic clock signal; a dummy bit line; a precharge circuit for precharging the dummy bit line and said plurality of bit lines to a precharge potential during a first half of a clock cycle; a plurality of discharge means respectively provided at the intersections of plurality of word lines and said dummy bit line, for discharging the dummy bit line, during the latter half of a clock cycle when the corresponding word lines are enabled by a row decoder; and a two input NOR gate, the first input receiving said clock signal and the second input receiving the potential of said dummy bit line, for generating a control signal for setting the latch circuits to the latch mode at the beginning of the first half of the clock cycle and for generating a control signal for switching the latch circuits from the latch mode to the through mode during the latter half of the clock cycle when the dummy bit line is discharged by one of the discharge means from the precharge potential to a predetermined potential.

Claim 12

A synchronous semiconductor memory, comprising: a plurality of bit lines; latch circuits, each of which is ocupled to receive the potential of a corresponding bit line and which can operate, in response to a control signal rising from a low level to a high level, in a through mode to output the potential of the corresonding bit line, or, in respone to the control signal falling from the high level to the low level, in a latch mode to latch and then output this potential; clock means for generating a cyclic clock signal; a dummy bit line; a precharge circuit for precharging the dummy bit line and said plurality of bit lines to a precharge potential during a first half of a clock cycle; a plurality of discharge means respectively provided at the intersections of plurality of word lines and said dummy bit line, for discharging the dummy bit line, during the latter half of a clock cycle when the corresponding word lines are enabled by a row decoder; and a two input NOR gate, the first input receiving said clock signal and the second input receiving the potential of said dummy bit line, for generating a control signal for setting the latch circuits to the latch mode at the beginning of the first half of the clock cycle and for generating a control signal for switching the latch circuits from the latch mode to the through mode during the latter half of the clock cycle when the dummy bit line is discharged by one of the discharge means from the precharge potential to a predetermined potential.

Claim 13

A synchronous semiconductor memory, comprising: a plurality of bit lines; latch circuits, each of which is coupled to receive the potential of a corresponding bit line and which can operate, in response to a control signal rising from a low level to a high level, in a through mode to output the potential of the corresponding bit line, or, in response to a control signal falling from the high level to the low level, in a latch mode to latch and then output this potential; clock means for generating a cyclic clock signal; a dummy bit line; a discharge circuit for discharging said dummy bit line and said plurality of bit lines to a discharge potential during a first half of a clock cycle; a plurality of charge means respectively provided at the intersections of a plurality of word lines and said dummy bit line for charging said dummy bit line during a latter half of the clock cycle when the corresponding word lines are enabled by a row decoder; and a two-input AND gate, the first input receiving a signal obtained by inverting the clock signal and the second input receiving the potential of said dummy bit line, generating a control signal for switching the latch circuits to the latch mode at the beginning of the first half of the clock cycle and for generating a control signal for switching the latch circuits from the latch mode to the through mode during the latter half of the clock cycle when said dummy bit line is charged by one of said charge means to have a potential raised from the discharge potential to a predetermined potential.

Claim 14

A synchronous semiconductor memory, comprising: a plurality of bit lines; latch circuits, each of which is coupled to receive the potential of a corresponding bit line and which can operate, in response to a control signal rising from a low level to a high level, in a through mode to output the potential of the corresponding bit line, or, in response to a control signal falling from the high level to the low level, in a latch mode to latch and then output this potential; clock means for generating a cyclic clock signal; a dummy bit line; a discharge circuit for discharging said dummy bit line and said plurality of bit lines to a discharge potential during a first half of a clock cycle; a plurality of charge means respectively provided at the intersections of a plurality of word lines and said dummy bit line for charging said dummy bit line during a latter half of the clock cycle when the corresponding word lines are enabled by a row decoder; and a two-input AND gate, the first input receiving a signal obtained by inverting the clock signal and the second input receiving the potential of said dummy bit line, generating a control signal for switching the latch circuits to the latch mode at the beginning of the first half of the clock cycle and for generating a control signal for switching the latch circuits from the latch mode to the through mode during the latter half of the clock cycle when said dummy bit line is charged by one of said charge means to have a potential raised from the discharge potential to a predetermined potential.