Glitch lockout circuit for memory array

Claim 1

A memory arrangement comprising an array of memory cells arranged to occupy rows and columns; a plurality of bit lines, each bit line associated with a separate one of the rows of said array of memory cells; a clock source responsive to an external master clock signal for generating as separate output signals a first clock phase and a second clock phase, said plurality of bit lines responsive to said first clock phase for precharging said plurality of bit lines to a predetermined value when said first clock phase is of a first binary value; a dummy bit line responsive to said first clock phase for precharging said dummy bit line wherein said dummy bit line precharges at a rate slower than said plurality of bit lines; latching means responsive to both said first clock phase and said dummy bit line for producing an output signal of a first binary value if and only if said first clock phase is in transition between said first binary value and the other binary value, and said dummy bit line is sufficiently precharged such that said bit lines are precharged to said predetermined value; and clock lockout means responsive to both said second clock phase and said latching means output signal allowing the propagation of said second clock phase to said memory array if and only if said latching means output signal is of said first binary value.