US4339766A
Expired / Lapsed
US
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Dummy columns for reducing pattern sensitivity in MOS/LSI dynamic RAM
Assignee: Texas Instruments Inc
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Filing: 1979-10-11
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Granted: 1982-07-13
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Expires: 1999-10-11
Abstract
Abstract An MOS/LSI type dynamic RAM with single 5V supply and grounded substrate employs a pair of dummy columns on each end of the cell array to prevent pattern sensitivity in testing. The dummy columns have capacitors which alternate between large and small so a given cell will always read a "1" or "0" upon refresh. These cells are not accessed in normal read or write cycles. Thus, regardless of the row addressed, one column line half on each side will go high and the other low. This shields the ends of the array from diffusing electrons (minority carriers).
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
115 words
A semiconductor memory device comprising an array of rows and columns of memory cells in a face of a semiconductor body, means for accessing data in said array, peripheral circuitry in said face spaced from the array, and a pair of dummy columns positioned in said face at each end of the array between the array and said circuitry to prevent diffusion of minority carriers from said circuitry to the memory, the dummy columns comprising a plurality of memory cells similar to that in said array of memory cells, said means for accessing not being connected to said dummy columns, each dummy column comprising a plurality of one-transistor cells having alternating large and small capacitors.
Claim 2
Dependent Claim
115 words
A semiconductor memory device comprising an array of rows and columns of memory cells in a face of a semiconductor body, means for accessing data in said array, peripheral circuitry in said face spaced from the array, and a pair of dummy columns positioned in said face at each end of the array between the array and said circuitry to prevent diffusion of minority carriers from said circuitry to the memory, the dummy columns comprising a plurality of memory cells similar to that in said array of memory cells, said means for accessing not being connected to said dummy columns, each dummy column comprising a plurality of one-transistor cells having alternating large and small capacitors.
Claim 3
Dependent Claim
21 words
A device according to claim 1 wherein adjacent dummy columns have large and small cells of opposite size in adjacent positions.
Claim 4
Dependent Claim
126 words
In a semiconductor memory device of the type having an array of rows and columns of memory cells in a face of a semiconductor body and peripheral circuitry in said face spaced from the array, a method of preventing minority carriers generated in the peripheral circuitry of the semiconductor memory array from reaching said memory cells in the array, comprising storing alternately "1's" and "0's" in cells of a pair of adjacent columns of said memory cells which are positioned at edges of the array nearest the peripheral circuitry, and repeatedly refreshing said "1's" and "0's" in the same cell positions in said adjacent columns during operating read or write cycles of said memory without accessing data in the cells of said pair of adjacent columns.
Claim 5
Dependent Claim
126 words
In a semiconductor memory device of the type having an array of rows and columns of memory cells in a face of a semiconductor body and peripheral circuitry in said face spaced from the array, a method of preventing minority carriers generated in the peripheral circuitry of the semiconductor memory array from reaching said memory cells in the array, comprising storing alternately "1's" and "0's" in cells of a pair of adjacent columns of said memory cells which are positioned at edges of the array nearest the peripheral circuitry, and repeatedly refreshing said "1's" and "0's" in the same cell positions in said adjacent columns during operating read or write cycles of said memory without accessing data in the cells of said pair of adjacent columns.
Claim 6
Dependent Claim
35 words
A method according to claim 3 wherein the step of repeatedly refreshing in said cells of said pair of adjacent columns includes storing only one logic state of "1" or "0" in a given cell.
Claim 7
Dependent Claim
36 words
A method according to claim 4 wherein the step of repeatedly refreshing includes the step of storing opposite logic states in cells which are adjacent one another in different ones of the pair of adjacent columns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-12 | 1986-01-11 | 1986-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-12 | 1990-01-11 | 1990-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-12 | 1994-01-11 | 1994-07-13 | $7700.00 | Window Closed / Lapsed |