Temperature compensated monolithic delay circuit

Claim 2

A temperature compensated time delay circuit of the type which can be fabricated in an integrated circuit comprising: (a) a capacitive element having first and second terminals and charged to a first voltage; (b) a field effect transistor having its source and drain respectively coupled to the first and second terminals of the capacitive element; (c) means for generating a bias voltage which is coupled to the gate of the field effect transistor such that the charge from the capacitive element flows through the field effect transistor at a rate determined principally by the characteristics of the field effect transistor and the bias voltage; and (d) means for temperature compensating said bias voltage wherein temperature induced changes in the field effect transistor are compensate for by appropriate changes in the bias voltage which compensation approximates the temperature variations of the surface mobility in said field effect transistor.

Claim 3

The delay circuit of claim 1 wherein said means for generating the bias voltage includes means for providing a series of forward biased p-n junction voltages.

Claim 4

A temperature compensating bias voltage circuit for use with a field effect transistor comprising: (a) means for providing an essentially temperature stable reference voltage; (b) a series connected plurality of bipolar transistor biased to operate in their active region in which the base terminal of the first transistor in the plurality of bipolar transistors is coupled to the reference voltage, each base terminal of the rest of the plurality of bipolar transistors is connected to the emitter terminal of the previous transistor of the series connected plurality of bipolar transistors and a bias voltage for use with the gate of a field effect transistor providing a constant current through the source-to-drain path thereof is present at the emitter terminal of the last transistor of the plurality of transistor, wherein the temperature variation of said bipolar transistors compensates for temperature variations in a field effect transistor providing constant current through the source-to-drain path thereof.

Claim 5

A temperature compensating bias voltage circuit for use with a field effect transistor comprising: (a) means for providing an essentially temperature stable reference voltage; (b) a series connected plurality of bipolar transistor biased to operate in their active region in which the base terminal of the first transistor in the plurality of bipolar transistors is coupled to the reference voltage, each base terminal of the rest of the plurality of bipolar transistors is connected to the emitter terminal of the previous transistor of the series connected plurality of bipolar transistors and a bias voltage for use with the gate of a field effect transistor providing a constant current through the source-to-drain path thereof is present at the emitter terminal of the last transistor of the plurality of transistor, wherein the temperature variation of said bipolar transistors compensates for temperature variations in a field effect transistor providing constant current through the source-to-drain path thereof.

Claim 6

The bias voltage circuit of claim 3 wherein the series connected plurality of bipolar transistors is comprised of at least three bipolar transistors.

Claim 7

The bias voltage circuit of claim 3 further including means for increasing the voltage at the terminal of the last transistor of the plurality of transistors by an amount equal to the threshold voltage of a field effect transistor.

Claim 10

A temperature compensated time delay circuit of the type which can be fabricated in an integrated circuit comprising: (a) capacitive means for providing an electrical capacitance; (b) bias voltage generation means for generating a bias voltage; (c) a field effect transistor having a gate terminal thereof coupled to said bias voltage generation means, and at least another terminal thereof coupled to said capacitive means for discharging thereof, such that the rate of change of the electrical charge on said capacitive means during at least a portion of the time delay is principally a function of the current through the field transistor and the characteristics of the field effect transistor and the bias voltage; (d) wherein temperature induced changes in the field effect transistor are the result of non-linear temperature variations in the mobility of the field effect transistor; (e) temperature compensation means for compensating said bias voltage generation means to vary said bias voltage over temperature in a non-linear manner opposite to the non-linear mobility variation to compensate therefore and maintain the current through the field effect transistor constant over temperature; and (f) wherein the temperature compensation means includes means for providing a series of forward biased p-n junction voltages.

Claim 11

A temperature compensated time delay circuit of the type which can be fabricated in an integrated circuit comprising: (a) capacitive means for providing an electrical capacitance; (b) bias voltage generation means for generating a bias voltage; (c) a field effect transistor having a gate terminal thereof coupled to said bias voltage generation means, and at least another terminal thereof coupled to said capacitive means for discharging thereof, such that the rate of change of the electrical charge on said capacitive means during at least a portion of the time delay is principally a function of the current through the field transistor and the characteristics of the field effect transistor and the bias voltage; (d) wherein temperature induced changes in the field effect transistor are the result of non-linear temperature variations in the mobility of the field effect transistor; (e) temperature compensation means for compensating said bias voltage generation means to vary said bias voltage over temperature in a non-linear manner opposite to the non-linear mobility variation to compensate therefore and maintain the current through the field effect transistor constant over temperature; and (f) wherein the temperature compensation means includes means for providing a series of forward biased p-n junction voltages.

Claim 12

A temperature compensated time delay circuit, comprising: a capacitor having first and second electrodes and charged to a first voltage; a field effect transistor having a source-to-drain path connected between one of said first and second electrodes and a reference voltage to discharge said capacitor to said reference voltage at a predetermined discharge rate, that is a function of the voltage applied to the gate thereof, said predetermined discharge rate having a non-linear response over temperature as a result of temperature variations of said transistor; bias generation means for generating said gate voltage to provide said predetermined discharge rate; and temperature compensation means for compensating said bias generation means to provide a compensated gate voltage over temperature that has a non-linear response over temperature opposite to the non-linear response of said transistor over temperature to control said transistor to maintain said predetermined discharge rate substantially constant over temperature.

Claim 13

A temperature compensated time delay circuit, comprising: a capacitor having first and second electrodes and charged to a first voltage; a field effect transistor having a source-to-drain path connected between one of said first and second electrodes and a reference voltage to discharge said capacitor to said reference voltage at a predetermined discharge rate, that is a function of the voltage applied to the gate thereof, said predetermined discharge rate having a non-linear response over temperature as a result of temperature variations of said transistor; bias generation means for generating said gate voltage to provide said predetermined discharge rate; and temperature compensation means for compensating said bias generation means to provide a compensated gate voltage over temperature that has a non-linear response over temperature opposite to the non-linear response of said transistor over temperature to control said transistor to maintain said predetermined discharge rate substantially constant over temperature.

Claim 14

The temperature compensation delay circuit of claim 8 wherein said predetermined discharge rate is a function of a constant current drain through said transistor wherein said temperature compensation means controls said bias generation means to maintain the current through said transistor constant at a temperature.

Claim 15

The temperature compensated delay circuit of claim 8 wherein the temperature variations of said transistor are a result of a non-linear temperature response of the mobility of said transistor wherein said temperature compensation means is operable to specifically compensate for the temperature variation in the mobility of said transistor to maintain a constant current through said transistor over temperature.

Claim 16

The temperature compensated delay circuit of claim 9 wherein said non-linear temperature response of the mobility of said transistor has a predetermined temperature profile and said temperature compensation means comprises: means for providing a profile over temperature that is opposite to the temperature profile of the discharge rate of current through the transistor as a result of non-linear variations of the mobility of the transistor over temperature; scaling means for scaling said opposite temperature profile for compensating said bias generation means to provide a constant current through the transistor over temperature.