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Method for fabricating bipolar semiconductor device

Assignee: Panasonic Holdings Corp
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Filing: 1987-10-13
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Granted: 1989-06-13
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Expires: 2007-10-13
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Abstract

Abstract In a method for fabricating a favorable bipolar semiconductor device in which the extrinsic base and emitter diffusion holes are formed in self-alignment, an optimum structure between the extrinsic base and instrinsic base is realized. By controlling the concentration of the impurities in the extrinsic base, the base contact and emitter region can be finely formed in self-alignment, and occurence of damage or contamination in the intrinsic base region is inhibited.

Inventors

  • 👤 Shuichi Kameyama
  • 👤 Tadao Komeda
  • 👤 Kazuhiro Kobushi
  • 👤 Hiroyuki Sakai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 06:32
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/124

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 384 words
A method of fabricating a bipolar semiconductor device comprising the steps of: selectively forming an insulation film around a prospective portion for forming a base on an epitaxial semiconductor layer of a first type of conductivity; forming an oxidation-resistant film material pattern on the prospective portion for forming a base; selectively leaving a mask material pattern on a prospective portion for forming an emitter on the oxidation-resistant film material pattern; selectively etching the oxidation-resistant film material pattern using the mask material pattern as a mask; forming a first semiconductor region as a part of the base by implanting impurity atoms of a second type of conductivity which is different from the first type of conductivity into the prospective portion for forming the base using the selectively formed insulation film and the mask material pattern as the mask; diffusing the impurity atoms of the second type of conductivity in a lateral direction; forming an insulation film on a surface of the first semiconductor region by selectively oxidizing using the oxidation-resistant film material pattern as the mask; forming a second semiconductor region of the second type of conductivity in the base region around the prospective portion for forming an emitter; exposing an emitter contact by removing the oxidation-resistant film material pattern used in the selective oxidation. forming a polycrystalline semiconductor electrode on the emitter contact; forming a third semiconductor region of the second type of conductivity as an intrinsic base beneath the prospective portion for forming the emitter by implanting impurity atoms of the second type conductivity into the polycrystalline semiconductor electrode and diffusing the impurity atoms of the second type of conductivity so as to prevent damage in the intrinsic base; and forming a fourth semiconductor region of the first type of conductivity as the emitter in the prospective portion or forming the emitter by implanting impurity atoms of the first type of conductivity into the polycrystalline semiconductor electrode an diffusing the impurity atoms of the first type of conductivity so as to prevent damage in the emitter; whereby the diffusion of the impurity atoms of the second type of conductivity of the first semiconductor region in the lateral direction of the emitter side is controlled by a dose of implantation to improve the electric breakdown voltage of the junction of the emitter and base.
Claim 2
Independent Claim 384 words
A method of fabricating a bipolar semiconductor device comprising the steps of: selectively forming an insulation film around a prospective portion for forming a base on an epitaxial semiconductor layer of a first type of conductivity; forming an oxidation-resistant film material pattern on the prospective portion for forming a base; selectively leaving a mask material pattern on a prospective portion for forming an emitter on the oxidation-resistant film material pattern; selectively etching the oxidation-resistant film material pattern using the mask material pattern as a mask; forming a first semiconductor region as a part of the base by implanting impurity atoms of a second type of conductivity which is different from the first type of conductivity into the prospective portion for forming the base using the selectively formed insulation film and the mask material pattern as the mask; diffusing the impurity atoms of the second type of conductivity in a lateral direction; forming an insulation film on a surface of the first semiconductor region by selectively oxidizing using the oxidation-resistant film material pattern as the mask; forming a second semiconductor region of the second type of conductivity in the base region around the prospective portion for forming an emitter; exposing an emitter contact by removing the oxidation-resistant film material pattern used in the selective oxidation. forming a polycrystalline semiconductor electrode on the emitter contact; forming a third semiconductor region of the second type of conductivity as an intrinsic base beneath the prospective portion for forming the emitter by implanting impurity atoms of the second type conductivity into the polycrystalline semiconductor electrode and diffusing the impurity atoms of the second type of conductivity so as to prevent damage in the intrinsic base; and forming a fourth semiconductor region of the first type of conductivity as the emitter in the prospective portion or forming the emitter by implanting impurity atoms of the first type of conductivity into the polycrystalline semiconductor electrode an diffusing the impurity atoms of the first type of conductivity so as to prevent damage in the emitter; whereby the diffusion of the impurity atoms of the second type of conductivity of the first semiconductor region in the lateral direction of the emitter side is controlled by a dose of implantation to improve the electric breakdown voltage of the junction of the emitter and base.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-06-12 1992-12-12 1993-06-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-06-12 1996-12-12 1997-06-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-06-12 2000-12-12 2001-06-13 $7700.00 Window Closed / Lapsed

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