Method for the formation of high density memory cells using ion implantation techniques

Claim 1

The method of forming a semiconductor structure comprising: forming a buried interconnect layer of a first conductivity type over a selected region of a substrate of a second conductivity type, said second conductivity type being opposite said first conductivity type; forming an epitaxial layer of said first conductivity type on said substrate such that a portion of said epitaxial layer overlies said buried interconnect layer; forming a thin first oxide layer on the top surface of said epitaxial layer; forming a nitride layer on said thin first oxide layer; forming grooves in portions of the epitaxial layer so as to form exposed recessed islands of semiconductor material; implanting a selected impurity into the exposed surface of said grooves thereby to form regions of said same conductivity type as said substrate but of higher impurity concentration than in said substrate to prevent leakage currents in the to-be-formed structure; oxidizing the silicon exposed by said grooves to form in said grooves second layers of thermally-grown silicon oxide to a selected thickness, said second layers of said thermally-grown silicon oxide directly contacting regions of said buried contact layer; removing selected portions of said nitride layer to expose regions of said thin first oxide layer covering portions of said island of semiconductor material in which further impurities of said first conductivity type are not to be added; oxidizing said wafer to form a relatively thick third oxide in those portions of semiconductor material covered by said regions of said thin first oxide layer exposed by the removal of portions of said nitride layer; removing all of the remainder of said nitride layer from said device; forming a base exclusion mask over said structure to prevent the implantation of impurities in the underlying semiconductor material covered by said base exclusion mask, said base exclusion mask covering at least the contact region to the buried interconnect layer and the base of the to-be-formed lateral transistor; ion implanting an impurity of said second conductivity type to form the emitter and collector of a lateral transistor and the base and base contact of a vertical transistor in those portions of said island of semiconductor material not covered by said base exclusion mask; removing the base exclusion mask and forming a second exclusion mask of a selected material thereby to prevent the further implantation of impurities in the emitter and collector of said lateral transistor and the base contact of said vertical transistor; ion implanting additional regions of first conductivity type in the regions covered by the thin first oxide and not covered by the second exclusion mask or said relatively thick third oxide, thereby to form the contact region to said buried interconnect layer and the emitters of a vertical transistor; removing the second exclusion mask from said structure; and etching the wafer for a sufficient time to remove the thin first oxide over the surface of the wafer but so as not to damage said second and third oxide, thereby to open selected contact areas to the active regions of said device.

Claim 2

The method of forming a semiconductor structure comprising: forming a buried interconnect layer of a first conductivity type over a selected region of a substrate of a second conductivity type, said second conductivity type being opposite said first conductivity type; forming an epitaxial layer of said first conductivity type on said substrate such that a portion of said epitaxial layer overlies said buried interconnect layer; forming a thin first oxide layer on the top surface of said epitaxial layer; forming a nitride layer on said thin first oxide layer; forming grooves in portions of the epitaxial layer so as to form exposed recessed islands of semiconductor material; implanting a selected impurity into the exposed surface of said grooves thereby to form regions of said same conductivity type as said substrate but of higher impurity concentration than in said substrate to prevent leakage currents in the to-be-formed structure; oxidizing the silicon exposed by said grooves to form in said grooves second layers of thermally-grown silicon oxide to a selected thickness, said second layers of said thermally-grown silicon oxide directly contacting regions of said buried contact layer; removing selected portions of said nitride layer to expose regions of said thin first oxide layer covering portions of said island of semiconductor material in which further impurities of said first conductivity type are not to be added; oxidizing said wafer to form a relatively thick third oxide in those portions of semiconductor material covered by said regions of said thin first oxide layer exposed by the removal of portions of said nitride layer; removing all of the remainder of said nitride layer from said device; forming a base exclusion mask over said structure to prevent the implantation of impurities in the underlying semiconductor material covered by said base exclusion mask, said base exclusion mask covering at least the contact region to the buried interconnect layer and the base of the to-be-formed lateral transistor; ion implanting an impurity of said second conductivity type to form the emitter and collector of a lateral transistor and the base and base contact of a vertical transistor in those portions of said island of semiconductor material not covered by said base exclusion mask; removing the base exclusion mask and forming a second exclusion mask of a selected material thereby to prevent the further implantation of impurities in the emitter and collector of said lateral transistor and the base contact of said vertical transistor; ion implanting additional regions of first conductivity type in the regions covered by the thin first oxide and not covered by the second exclusion mask or said relatively thick third oxide, thereby to form the contact region to said buried interconnect layer and the emitters of a vertical transistor; removing the second exclusion mask from said structure; and etching the wafer for a sufficient time to remove the thin first oxide over the surface of the wafer but so as not to damage said second and third oxide, thereby to open selected contact areas to the active regions of said device.