Patent US4836885A successfully refreshed from Google Patents.
US4836885A
Expired / Lapsed
US
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Planarization process for wide trench isolation
Assignee: International Business Machines Corp
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Filing: 1988-05-03
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Granted: 1989-06-06
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Expires: 2008-05-03
Abstract
Abstract A method of planarizing wide dielectric filled isolation trenches formed in the surface of a semiconductor surface is described. A self aligned mask is formed on the thick conformal layer of dielectric in the depressions over the wide trenches to protect the dielectric in those trenches from etching during planarization steps. The mask material is chosen to have etch characteristics different from the dielectric layer and a subsequent planarizing organic layer to allow selective etching of the mask material or dielectric without etching the other materials in the structure.
Inventors
- 👤 Charles P. Breiten
- 👤 David Stanasolovich
- 👤 Jacob F. Theisen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:37
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W10/01; H10W10/011; H10W10/014; H10W10/0143
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
191 words
A method of planarizing wide dielectric filled trenches in a surface of a semiconductor substrate comprising the steps of: depositing a first conformal dielectric layer in said wide trenches and over the surface of said semiconductor substrate, forming depressions on the surface of said first layer over said wide trenches, depositing a second layer having etch characteristics which differ substantially from said first layer, on said first layer, applying a thick planarizing layer on said second layer, etching said thick planarizing layer until the portions of said second layer disposed over said surface of said semiconductor substrate are exposed but leaving portions of said thick planarizing layer in said depressions disposed over the wide trenches, etching said exposed portions of said second layer in a etching medium with a high selectivity between said second layer to said first layer, leaving masking areas of said second layer over said first layer deposited in said wide trenches, etching said first layer in an etching medium with a high selectivity between said first layer to said second layer to said surface of said semiconductor substrate, and removing said masking areas of said second layer.
Claim 2
Independent Claim
191 words
A method of planarizing wide dielectric filled trenches in a surface of a semiconductor substrate comprising the steps of: depositing a first conformal dielectric layer in said wide trenches and over the surface of said semiconductor substrate, forming depressions on the surface of said first layer over said wide trenches, depositing a second layer having etch characteristics which differ substantially from said first layer, on said first layer, applying a thick planarizing layer on said second layer, etching said thick planarizing layer until the portions of said second layer disposed over said surface of said semiconductor substrate are exposed but leaving portions of said thick planarizing layer in said depressions disposed over the wide trenches, etching said exposed portions of said second layer in a etching medium with a high selectivity between said second layer to said first layer, leaving masking areas of said second layer over said first layer deposited in said wide trenches, etching said first layer in an etching medium with a high selectivity between said first layer to said second layer to said surface of said semiconductor substrate, and removing said masking areas of said second layer.
Claim 3
Dependent Claim
40 words
The method recited in claim 1 which further comprises the steps of: depositing a second layer of said conformal dielectric layer after removing said masking areas of said second layer, and planarizing said second layer of said conformed dielectric layer.
Claim 4
Dependent Claim
54 words
The method recited in claim 2 wherein the planarizing step comprises: applying a thick planarizing layer on said second layer of said conformal dielectric layer, and etching said thick planarizing layer and said second layer of said conformal dielectric layer in a nonselective 1:1 etch rate ratio to said surface of said semiconductor substrate.
Claim 5
Dependent Claim
49 words
The method recited in claim 2 wherein the planarizing step comprises: applying a thick planarizing layer on said second layer of said conformal dielectric layer, and ion beam milling said thick planarizing layer and said second layer of said conformal dielectric layer to said surface of said semiconductor substrate.
Claim 6
Dependent Claim
23 words
The method recited in claim 1 wherein said wide trenches have widths greater than twice the thickness of said first conformal dielectric layer.
Claim 7
Dependent Claim
21 words
The method recited in claim 1 where said first layer is selected from the group of silicon dioxide and silicon nitride.
Claim 8
Dependent Claim
22 words
The method recited in claim 1 where said second layer is selected from the group of silicon nitride, silicon oxide, an polysilicon.
Claim 9
Dependent Claim
25 words
The method recited in claim 1 where said thick planarizing layer is selected from the group of photoresist, polyimide, resin glass, or doped reflowable glass.
Claim 10
Independent Claim
180 words
A method of planarizing wide dielectric filled trenches in a surface of a silicon substrate comprising the steps of: depositing a first conformal silicon dioxide layer in said wide trenches and over the surface of said silicon substrate, forming depressions on the surface of said first layer over said wide trenches, depositing a second layer of silicon nitride on said first layer, applying a thick planarizing layer of photoresist on said second layer, etching said photoresist until the portions of said second layer disposed over said surface of said silicon substrate are exposed but leaving photoresist in said depressions disposed over the wide trenches, etching said exposed portions of said second layer in a etching medium with a high selectivity between said second layer to said first layer, leaving masking areas of said second layer over said first layer deposited in said wide trenches, etching said first layer in an etching medium with a high selectivity between said first layer to said second layer to said surface of said silicon substrate, and removing said masking areas of said second layer.
Claim 11
Independent Claim
180 words
A method of planarizing wide dielectric filled trenches in a surface of a silicon substrate comprising the steps of: depositing a first conformal silicon dioxide layer in said wide trenches and over the surface of said silicon substrate, forming depressions on the surface of said first layer over said wide trenches, depositing a second layer of silicon nitride on said first layer, applying a thick planarizing layer of photoresist on said second layer, etching said photoresist until the portions of said second layer disposed over said surface of said silicon substrate are exposed but leaving photoresist in said depressions disposed over the wide trenches, etching said exposed portions of said second layer in a etching medium with a high selectivity between said second layer to said first layer, leaving masking areas of said second layer over said first layer deposited in said wide trenches, etching said first layer in an etching medium with a high selectivity between said first layer to said second layer to said surface of said silicon substrate, and removing said masking areas of said second layer.
Claim 12
Dependent Claim
27 words
The method recited in claim 6 wherein said exposed areas of said second layer are plasma etched in an ambient of CHF 3 and O 2 .
Claim 13
Dependent Claim
23 words
The method recited in claim 6 wherein said first layer is plasma etched in an ambient of CHF 3 and CF 4 .
Claim 14
Dependent Claim
36 words
The method recited in claim 6 which further comprises the steps of: depositing a second layer of silicon dioxide after removing said masking areas of said second layer, and planarizing said second layer of silicon dioxide.
Claim 15
Independent Claim
173 words
A method for making a semiconductor structure which comprises the steps of: etching a pattern of wide and narrow trenches into a surface of a semiconductor substrate, depositing a first conformal dielectric layer over said surface and in said wide and narrow trenches forming depressions on the surface of said first conformal dielectric layer over said wide trenches, depositing a second layer having etch characteristics which differ substantially from said first layer on said first layer; applying a thick planarizing layer on said second layer, etching said thick planarizing layer until the portions o said second layer disposed over said narrow trenches and over said surface of said semiconductor are exposed, but leaving portions of said thick planarizing layer in the depressions disposed over said wide trenches, selectively etching said exposed portions of said second layer to expose portions of said first layer disposed over said narrow trenches and said surface of said semiconductor substrate, selectively etching said exposed portions of said first layer, and removing said masking areas of said second layer.
Claim 16
Independent Claim
173 words
A method for making a semiconductor structure which comprises the steps of: etching a pattern of wide and narrow trenches into a surface of a semiconductor substrate, depositing a first conformal dielectric layer over said surface and in said wide and narrow trenches forming depressions on the surface of said first conformal dielectric layer over said wide trenches, depositing a second layer having etch characteristics which differ substantially from said first layer on said first layer; applying a thick planarizing layer on said second layer, etching said thick planarizing layer until the portions o said second layer disposed over said narrow trenches and over said surface of said semiconductor are exposed, but leaving portions of said thick planarizing layer in the depressions disposed over said wide trenches, selectively etching said exposed portions of said second layer to expose portions of said first layer disposed over said narrow trenches and said surface of said semiconductor substrate, selectively etching said exposed portions of said first layer, and removing said masking areas of said second layer.
Claim 17
Dependent Claim
40 words
The method recited in claim 13 which further comprises the steps of: depositing a second layer of said conformal dielectric layer after removing said masking areas of said second layer, and planarizing said second layer of said conformal dielectric layer.
Claim 18
Dependent Claim
54 words
The method recited in claim 14 wherein the planarizing step comprises: applying a thick planarizing layer on said second layer of said conformal dielectric layer, and etching said thick planarizing layer and said second layer of said conformal dielectric layer in a nonselective 1:1 etch rate ratio to said surface of said semiconductor substrate.
Claim 19
Dependent Claim
49 words
The method recited in claim 14 wherein the planarizing step comprises: applying a thick planarizing layer on said second layer of said conformal dielectric layer, and ion beam milling said thick planarizing layer and said second layer of said conformal dielectric layer to said surface of said semiconductor substrate.
Claim 20
Dependent Claim
36 words
The method recited in claim 13 wherein said wide trenches have widths greater than twice the thickness of said conformal dielectric layer and said narrow trenches have widths less than the widths of said wide trenches.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-05 | 1992-12-05 | 1993-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-05 | 1996-12-05 | 1997-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-05 | 2000-12-05 | 2001-06-06 | $7700.00 | Window Closed / Lapsed |