Digital engine analyzer

Claim 1

An engine analyzer for analyzing an internal combustion engine that produces analog signals, said engine analyzer comprising an analog to digital converter for converting the analog signals into digital signals at a variable sampling rate, memory means including first and second memory banks for storing the digital signals, memory write means coupled to said memory means for writing the digital signals into said memory means at a variable writing rate which corresponds to the rate at which the digital signals are being produced, memory readout means coupled to said memory means for reading the digital signals from said memory means, control means for controlling said memory banks, said memory write means and said memory readout means to enable digital signals to be written into said first memory bank while digital signals are read from said second memory bank and to enable digital signals to be read from said first memory bank while digital signals are written into said second memory bank, a cathode ray tube including a screen and an electron beam which is swept across said screen, said control means being coupled to the engine to receive information on the speed of the engine to cause the sampling rate and the writing rate to be dependent on the engine speed and to vary the rates automatically in correspondence with changes in engine speed, and said control means controlling the readout rate to correspond with the rate at which the beam is swept across the screen, the rate at which digital signals are read out of said memory means being many times greater than the rate at which digital signals are written into said memory means, said screen being defined by a plurality of rows and a plurality of columns, the electron beam being selectively operable to illuminate selected points at the intersections of the rows and the columns, each digital signal identifying the row location of a selected point in a different one of the columns (R-CC), the electron beam scanning said screen along a row in one row after the next, row monitoring means for monitoring the row in which the electron beam is sweeping at an instant of time (R-S), latching means having a clock input coupled to a source of clock signals and a signal input coupled to said memory means for receiving the R-CC information on a row containing a data point in a given column and latching it until R-CC information for the next column is read out so as to provide information on the row containing a data point in the immediately preceding column (R-PC), and circuit means coupled to said row monitoring means and to said memory means and to said latching means and being responsive to R-S and R-CC and R-PC information to provide a screen energizing signal at each intersection corresponding to the location of a digital signal and to each intersection in a column below a digital signal intersection in such column and above a digital signal intersection in the immediately preceding column and to each intersection in a column above a digital signal intersection in such column and below a digital signal intersection in an immediately preceding column, thereby giving continuity to the waveform displayed on said screen.