Speech processor for changing voice pitch

Claim 2

Apparatus for processing speech signals, comprising: A. an input terminal for receiving said speech signals; B. an analog-to-digital converter coupled to said input terminal; C. first and second storage means coupled to said analog-todigital converter; D. means for alternately reading said signals into said first and second storage means at a first rate; E. an output terminal; F. means for alternately reading out said first and second storage means at a second rate, said signals being read out at said second rate being coupled to said output terminal; and G. a digital-to-analog converter coupled to the output of said storage means.

Claim 3

Apparatus as defined in claim 1 wherein said speech signals are that of a diver speaking in a helium-oxygen atmosphere.

Claim 4

each coupled to said conversion means at said signal input terminal,

Claim 5

each coupled to said conversion means at said signal input terminal,

Claim 6

each having m storage positions, and

Claim 7

each having m storage positions, and

Claim 8

Apparatus as defined in claim 1 wherein said speech signals are that of a normal voice recording played back at a higher speed than the original recording speed.

Claim 9

Apparatus as defined in claim 1 wherein said first and second storage means comprises first and second shift registers.

Claim 10

each having a clock input for shifting the signal into said signal input terminal through each of said m storage positions, and out of said signal output terminal; E. means for sensing the occurrence of m of said first clock pulses; F. means for alternately coupling said first clock pulses to said clock input of said first register means and then to said clock input of said second register means each time said sensing means senses the occurrence of m of said first clock pulses; G. means for alternately coupling said second clock pulses to said clock input of one of said register means which is not connected to said first clock pulses; H. means for coupling said signal output terminal of one of said register means which has its clock input coupled to said second clock pulses, to said processor output terminal, and I. digital-to-analog conversion means coupling said shift register means to said processor output terminal whereby the signal is loaded into said register means at a higher rate than the signal is unloaded from said register means and whereby the signal at said processor output terminal is proportional to the ratio of frequencies of the second clock pulses over the first clock pulses times that amount of signal in the signal from the conversion means.

Claim 11

each having a clock input for shifting the signal into said signal input terminal through each of said m storage positions, and out of said signal output terminal; E. means for sensing the occurrence of m of said first clock pulses; F. means for alternately coupling said first clock pulses to said clock input of said first register means and then to said clock input of said second register means each time said sensing means senses the occurrence of m of said first clock pulses; G. means for alternately coupling said second clock pulses to said clock input of one of said register means which is not connected to said first clock pulses; H. means for coupling said signal output terminal of one of said register means which has its clock input coupled to said second clock pulses, to said processor output terminal, and I. digital-to-analog conversion means coupling said shift register means to said processor output terminal whereby the signal is loaded into said register means at a higher rate than the signal is unloaded from said register means and whereby the signal at said processor output terminal is proportional to the ratio of frequencies of the second clock pulses over the first clock pulses times that amount of signal in the signal from the conversion means.

Claim 12

Apparatus as defined in claim 4 wherein said readin and readout means includes: A. clock means for generating pulses at a first frequency and for generating pulses at a second frequency, said second frequency being lower in frequency than said first frequency; and B. first switch means for coupling said pulses of said first frequency to the clock input of said first shift register whereby signals are loaded into said first shift register at said first frequency and for simultaneously coupling said pulses of said second frequency to the clock input of said second shift register whereby signals are unloaded from said second shift register at said second frequency.

Claim 13

Apparatus as defined in claim 5 wherein said readin and readout means further include: A. means for sensing the loading of a predetermined amount of signal into said first shift register; B. means connecting said sensing means to said first switch means for toggling said first switch means upon said sensing such that said pulses of said first frequency are coupled to the clock input of said second shift register whereby signals are loaded into said second shift register at said first frequency and such that said pulses of said second frequency are coupled to the clock input of said first shift register whereby signals are unloaded from said first shift register at said second frequency; and C. second switch means for coupling the register being unloaded to said output terminal.

Claim 14

Apparatus as defined in claim 6 wherein said second switch means is toggled by said sensing means.

Claim 15

Apparatus as defined in claim 6 wherein said second frequency of said clock means is variable.

Claim 16

Apparatus as defined in claim 6 wherein said analog-to-digital converter includes a clipping network.

Claim 17

Apparatus as defined in claim 6 wherein said analog-to-digital converter produces a binary pulse pattern of the speech signals on n output lines.

Claim 18

Apparatus as defined in claim 6, further including: a filter network coupled to receive a signal from said digital-to-analog converter.

Claim 19

Apparatus as defined in claim 6 wherein said analog-to-digital converter includes a delta modulator.

Claim 20

Apparatus as defined in claim 12 wherein said first and second shift registers are each comprised of n parallel connected shift registers, each of which n parallel shift registers is coupled to a corresponding line of said n output lines.

Claim 21

Apparatus for processing speech signals, comprising: A. an input terminal for receiving said speech signals; B. means for converting said speech signals into digital signals; C. a pair of shift registers coupled to receive said digital signals; D. means for alternately clocking said digital signals into one of said shift registers at a first frequency; E. means for alternately clocking said digital signals out of the other of said shift registers at a second frequency which is lower than said first frequency; and F. means for converting said digital signals clocked out of said shift registers at said second frequency to analog form.

Claim 22

Apparatus for processing speech signals, comprising: A. an input terminal for receiving said speech signals; B. means for converting said speech signals into digital signals; C. a pair of shift registers coupled to receive said digital signals; D. means for alternately clocking said digital signals into one of said shift registers at a first frequency; E. means for alternately clocking said digital signals out of the other of said shift registers at a second frequency which is lower than said first frequency; and F. means for converting said digital signals clocked out of said shift registers at said second frequency to analog form.

Claim 23

Signal-processing apparatus having a processor output terminal, said apparatus comprising: A. analog-to-digital conversion means; B. means for generating first clock pulses at a first frequency; C. means for generating second clock pulses at a second frequency, said second frequency being lower in frequency than said first frequency; D. first and second shift register means

Claim 24

Signal-processing apparatus having a processor output terminal, said apparatus comprising: A. analog-to-digital conversion means; B. means for generating first clock pulses at a first frequency; C. means for generating second clock pulses at a second frequency, said second frequency being lower in frequency than said first frequency; D. first and second shift register means

Claim 25

Apparatus as defined in claim 15 wherein said signal is that of a diver submerged in water whereby said signal is made intelligible.

Claim 26

Apparatus as defined in claim 15 wherein sAid signal is that of a normal voice recording played back at higher speed thereby resulting in an intelligible, speed hearing playback.

Claim 27

Apparatus as defined in claim 15 wherein A. said analog-to-digital converter produces a binary pulse pattern of said signal on n output lines; and B. said first and second shift register means are each comprised of n parallel connected shift registers, each of which n parallel shift registers is coupled to a corresponding line of said n output lines.

Claim 28

Apparatus as defined in claim 18 wherein said means for converting a digital signal to an analog signal includes a filter network for further restoring said signal to analog form.