US4142146A
Expired / Lapsed
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Digital apparatus for waveform measurement
Assignee: Thermo Electron Scientific Instruments LLC
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Filing: 1975-07-07
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Granted: 1979-02-27
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Expires: 1995-07-07
Abstract
Abstract Digital instrumentation for waveform measurement including method and apparatus for providing irregularly spaced sampling times to prevent misleading visual patterns of coordinate points due to the presence of signal frequencies above the Nyquist frequency. The method and apparatus includes means for plotting coordinate points having abscissa positions corrected according to actual irregular sampling times, method and apparatus whereby irregularities are repeated for each signal sweep, and method and apparatus utilizing a bit reversal system to achieve the irregularly spaced sampling times.
Inventors
- 👤 Robert W. Schumann
- 👤 Gary L. Wells
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:49
CPC Classifications
G; G01; G01R; G01R13/00; G01R13/02
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
63 words
In waveform measurement apparatus including means for taking a time sequence of voltage samples of a signal, and means for displaying the sampled voltages to provide a representation of the signal, the improvement comprising: means for taking the voltage samples at random times for providing a scattered display to prevent aliasing when the signal includes frequency components greater than half the sampling frequency.
Claim 2
Dependent Claim
63 words
In waveform measurement apparatus including means for taking a time sequence of voltage samples of a signal, and means for displaying the sampled voltages to provide a representation of the signal, the improvement comprising: means for taking the voltage samples at random times for providing a scattered display to prevent aliasing when the signal includes frequency components greater than half the sampling frequency.
Claim 3
Dependent Claim
40 words
The apparatus of claim 1 including: means for displaying the randomly timed samples at times related to actual sampling time, for providing a display representative of the signal when the signal includes frequency components less than half the sampling frequency.
Claim 4
Dependent Claim
81 words
In digital apparatus for analog waveform measurement including signal input means, signal sampling means for taking a plurality of voltage samples of a signal, memory means for storing the sampled voltages, digital address counter means for controlling the memory means, and coordinate display means connected to the memory means for displaying sampled voltages, the improvement comprising: timing control means connected to the sampling means for taking the plurality of sample voltages at sequential irregularly spaced time intervals, to prevent aliasing effects.
Claim 5
Dependent Claim
81 words
In digital apparatus for analog waveform measurement including signal input means, signal sampling means for taking a plurality of voltage samples of a signal, memory means for storing the sampled voltages, digital address counter means for controlling the memory means, and coordinate display means connected to the memory means for displaying sampled voltages, the improvement comprising: timing control means connected to the sampling means for taking the plurality of sample voltages at sequential irregularly spaced time intervals, to prevent aliasing effects.
Claim 6
Dependent Claim
32 words
The apparatus of claim 3 in which: the timing control means is connected to the address counter means for deriving the irregular time intervals from the states of the address counter means.
Claim 7
Dependent Claim
38 words
The apparatus of claim 4 in which: the timing control means includes further counter means connected to the address counter means for deriving the irregular time intervals by bit reversal of the states of the address counter means.
Claim 8
Dependent Claim
31 words
The apparatus of claim 3 including: means connected to the display means for providing abscissa values for each displayed sampled voltage related to the actual time the voltage sample was taken.
Claim 9
Dependent Claim
39 words
The apparatus of claim 5 including: means connected to the address counter means and display means for providing abcissa values for each displayed sampled voltage related to a bit reversal of the corresponding state of the address counter means.
Claim 10
Dependent Claim
144 words
In digital apparatus for analog waveform measurement including signal input means, signal sampling means for taking a plurality of voltage samples of a signal, memory means for storing the sampled voltages, address counter means for controlling the memory means, and coordinate display means connected to the memory means for displaying sampled voltages, the improvement comprising: timing control means connected to the sampling means for taking the plurality of sample voltages at irregularly spaced time intervals, to prevent aliasing effects; further counter means connected to the address counter means, means for entering at least a portion of the state of the address counter means into the further counter means in reverse order of bit significance; and means connecting the further counter means to the timing means for controlling the spaced time intervals between sample voltages according to the count time of the further counter means.
Claim 11
Dependent Claim
144 words
In digital apparatus for analog waveform measurement including signal input means, signal sampling means for taking a plurality of voltage samples of a signal, memory means for storing the sampled voltages, address counter means for controlling the memory means, and coordinate display means connected to the memory means for displaying sampled voltages, the improvement comprising: timing control means connected to the sampling means for taking the plurality of sample voltages at irregularly spaced time intervals, to prevent aliasing effects; further counter means connected to the address counter means, means for entering at least a portion of the state of the address counter means into the further counter means in reverse order of bit significance; and means connecting the further counter means to the timing means for controlling the spaced time intervals between sample voltages according to the count time of the further counter means.
Claim 12
Dependent Claim
48 words
The apparatus of claim 8 including: means connected to the display means for summing each address counter state with the reverse order portion put into the further counter means, for providing abscissa values for each displayed sampled voltage related to the actual irregular time the sample was taken.
Claim 13
Dependent Claim
82 words
In the method of measuring waveforms with digital apparatus comprising the steps of taking a sequence of voltage samples of a signal, storing the sampled voltages, and displaying the sampled voltages on a coordinate display, the improvement comprising: controlling the storing and displaying of sampled voltages with a counter; deriving irregular time intervals from the states of the counter; taking the voltage samples at said irregular time intervals; and displaying the voltage samples at times related to the irregular times between intervals.
Claim 14
Dependent Claim
82 words
In the method of measuring waveforms with digital apparatus comprising the steps of taking a sequence of voltage samples of a signal, storing the sampled voltages, and displaying the sampled voltages on a coordinate display, the improvement comprising: controlling the storing and displaying of sampled voltages with a counter; deriving irregular time intervals from the states of the counter; taking the voltage samples at said irregular time intervals; and displaying the voltage samples at times related to the irregular times between intervals.
Claim 15
Dependent Claim
26 words
The method of claim 10 including the step of: altering the bit order of the state of the binary counter to derive the irregular time intervals.
Claim 16
Dependent Claim
24 words
The method of claim 10 including the step of: repeating the same set of irregularly spaced time intervals for each sequence of voltage samples.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-26 | 1982-08-28 | 1983-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-26 | 1986-08-28 | 1987-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-26 | 1990-08-28 | 1991-02-27 | $7700.00 | Window Closed / Lapsed |