US3768004A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Engine timing computer
Assignee: AUTECH MEASUREMENT SYSTEMS Inc
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Filing: 1972-01-20
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Granted: 1973-10-23
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Expires: 1992-01-20
Abstract
Abstract There is disclosed a method and apparatus for internal combustion engine timing based on measurement of the advance or retard of the firing of each spark plug with respect to a reference derived from the top dead center position of the piston for the number one cylinder. The engine timing is adjusted so that the average value of the advance or retard for all plugs equals a predetermined design value. A variable frequency oscillator is phase-locked by signals representing individual spark plug firing to operate at a frequency of 3,600 pulses per engine revolution. A reference related to the top dead center position of piston for the first cylinder is determined by sensing a notch in the engine damper or fan pulley, and is used to produce a series of pseudo damper pulses offset from the top dead center positions of the various pistons by 45 degrees by dividing the output of the variable frequency oscillator and selecting pulses to define the pseudo damper pulse interval based on the number of cylinders in the engine being timed. Timing measurement is achieved by counting the number of pulses between firing of a plug and the associated pseudo damper pulse over several complete engine operating cycles, averaging the result and removing the 45 degree offset. Digital display, printout, upper and lower limit computation and actual engine RPM measurements are also provided.
Inventors
- 👤 A Abnett
- 👤 R Boley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:51
CPC Classifications
F; F02; F02P; F02P17/00; F02P17/02; F02P17/04
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
541 words
In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, said means for establishing said timing interval comprising a logic circuit having a first input receiving said reference pulses, and a second input receiving said ignition pulses; selection means for establishing retard and advance modes of operation; said logic circuit being responsive to selection of the advance mode to initiate a timing interval in response to an ignition pulse, and to terminate said timing interval in response to the next reference pulse, said logic means being further responsive to selection of the retard mode of operation to initiate a timing interval in response to a reference pulse, and to terminate said timing interval in response to the next ignition pulse, said logic circuit including a set-reset flipflop; means responsive to selection of the advance mode of operation for coupling said ignition pulses to the set input of said flip-flop, and the reference pulses to the reset input of said flip-flop, and further being responsive to selection of the retard mode for coupling the reference pulses to the set input of said flip-flop, and the ignition pulses to the reset input of said flip-flop; said logic further including means for coupling one output of said flip-flop to said gating means to actuate the same when said flip-flop is set.
Claim 2
Dependent Claim
541 words
In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, said means for establishing said timing interval comprising a logic circuit having a first input receiving said reference pulses, and a second input receiving said ignition pulses; selection means for establishing retard and advance modes of operation; said logic circuit being responsive to selection of the advance mode to initiate a timing interval in response to an ignition pulse, and to terminate said timing interval in response to the next reference pulse, said logic means being further responsive to selection of the retard mode of operation to initiate a timing interval in response to a reference pulse, and to terminate said timing interval in response to the next ignition pulse, said logic circuit including a set-reset flipflop; means responsive to selection of the advance mode of operation for coupling said ignition pulses to the set input of said flip-flop, and the reference pulses to the reset input of said flip-flop, and further being responsive to selection of the retard mode for coupling the reference pulses to the set input of said flip-flop, and the ignition pulses to the reset input of said flip-flop; said logic further including means for coupling one output of said flip-flop to said gating means to actuate the same when said flip-flop is set.
Claim 3
Dependent Claim
36 words
A timing computer as defined in claim 1 wherein said control counting means comprises a counter, and means for operating said counter in response to transition of said flip-flop from the set to the reset condition.
Claim 4
Dependent Claim
381 words
In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said said storage means, said control means including calibrating means responsive to passage of a predetermined number of timing intervals to reduce the count stored in said main counter by a number corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston.
Claim 5
Dependent Claim
381 words
In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said said storage means, said control means including calibrating means responsive to passage of a predetermined number of timing intervals to reduce the count stored in said main counter by a number corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston.
Claim 6
Dependent Claim
115 words
A timing computer as defined in claim 3 further including a calibration counter, means responsive to said control signal to establish a calibration interval; gating means coupling said master pulse train to the input of said calibration counter, said gating means being operative during said calibration interval to pass said master pulses to said calibration counter; means for reducing the count in said main counter in synchronism with the operation of said calibration counter; means responsive to a predetermined count in said calibration counter to terminate said calibration interval; means responsive to termination of said calibration interval to reset said calibration counter, whereby the count in said main counter is reduced by said predetermined number.
Claim 7
Dependent Claim
32 words
A timing computer as defined in claim 4 further including means responsive to establishment of said calibration interval to inhibit the establishment of further timing intervals until said calibration interval is completed.
Claim 8
Dependent Claim
455 words
In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means to counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, said control counting means comprising a second counter; means responsive to occurrence of a timing interval to increase the count in said second counter; means responsive to said second counter reaching a predetermined count indicating occurrence of the corresponding number of counting intervals for said main counter to generate said control signal; means responsive to said control signal and to said master pulse train to generate a second control signal a predetermined number of master pulses thereafter, and to generate a third control signal a predetermined number of master pulses after said second control signal; means for coupling said second control signal to actuate said angle readout storage means; and Means responsive to said third control signal for resetting said main counter.
Claim 9
Dependent Claim
455 words
In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means to counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, said control counting means comprising a second counter; means responsive to occurrence of a timing interval to increase the count in said second counter; means responsive to said second counter reaching a predetermined count indicating occurrence of the corresponding number of counting intervals for said main counter to generate said control signal; means responsive to said control signal and to said master pulse train to generate a second control signal a predetermined number of master pulses thereafter, and to generate a third control signal a predetermined number of master pulses after said second control signal; means for coupling said second control signal to actuate said angle readout storage means; and Means responsive to said third control signal for resetting said main counter.
Claim 10
Dependent Claim
48 words
A timing computer as defined in claim 6 wherein said means to generate said second and third control signals comprises a third counter, means for coupling said master pulse train to operate said third counter, and means responsive to said first control signal to reset said third counter.
Claim 11
Dependent Claim
49 words
A timing computer as defined in claim 7 wherein said means coupling said master pulse train to said third counter comprises a frequency divider having a counter base sufficiently large that the complete operating cycle of said third counter is shorter than the operating cycle for said second counter.
Claim 12
Dependent Claim
48 words
A timing computer as defined in claim 7 further including calibration means responsive to said control signal to reduce the count stored in said main counter by a number corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston.
Claim 13
Dependent Claim
107 words
A timing computer as defined in claim 9 wherein said calibration means comprises a fourth counter; means responsive to said control signal to establish a calibration interval; gating means coupling said master pulse train to the input of said fourth counter, said gating means being operative during said calibration interval to pass said master pulse train to said fourth counter; means for reducing the count in said main counter in synchronism with the operation of said fourth counter; means responsive to a predetermined count in said fourth counter to terminate said calibration interval; and means responsive to termination of said calibration interval to reset said fourth counter.
Claim 14
Dependent Claim
45 words
A timing computer as defined in claim 10 further including means responsive to establishment of said calibration interval to prevent the establishment of further timing intervals for said main counter, and to inhibit operation of said third counter until said calibration interval has been terminated.
Claim 15
Dependent Claim
38 words
A timing computer as defined in claim 11 wherein said third counter is operative to generate said second control signal a predetermined number of counts after operation thereof is permitted to resume after termination of said calibration interval.
Claim 16
Dependent Claim
381 words
In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of Said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, and further including engine speed computing means; limit logic to establish a maximum acceptable engine speed; means responsive to the sensing of an engine speed exceeding the preset limit to generate a limit signal; and means responsive to said limit signal to disable said timing angle readout unit.
Claim 17
Dependent Claim
381 words
In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of Said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, and further including engine speed computing means; limit logic to establish a maximum acceptable engine speed; means responsive to the sensing of an engine speed exceeding the preset limit to generate a limit signal; and means responsive to said limit signal to disable said timing angle readout unit.
Claim 18
Dependent Claim
134 words
A timing computer as defined in claim 13 wherein said engine speed computing means comprises a counter, means coupling said master pulse train to operate said counter; engine speed readout means comprising means for storing a count contained in said engine speed counter, and visual display means for said stored count; clock means for producing a periodic signal defining an engine speed computation interval; means responsive to the end of a computation cycle to generate a further control signal; means responsive to said first control signal for operating said storage means to store the count then contained in said engine speed counter; further means responsive to said further control signal to generate an additional control signal a predetermined time thereafter; and means responsive to said additional control signal to reset said engine speed counter.
Claim 19
Dependent Claim
71 words
A timing computer as defined in claim 14 wherein said coupling means comprises a frequency divider, the counting base of said divider and the duration of said computing interval being so selected in relation to the number of master pulses per engine revolution that the count contained in said speed counter at the end of the computation interval is equal to the average engine speed in RPM during the computing interval.
Claim 20
Dependent Claim
193 words
A timing computer as defined in claim 14 wherein said limit logic comprises first circuit means coupled to said engine speed counter, a plurality of set-reset flip-flops, said first circuit means being operative to set said flip-flops in a predetermined order as the count in said speed counter increases by predetermined increments whereby, at the end of said computation interval one or more flip-flops are set indicating the number of incremental advances of said engine speed counter during said computation interval; latching means having individual latch circuits connected to the outputs of respective ones of said flip-flops; said latch circuits being responsive to said further control signal to store respective signals indicative of the states of the associated flip-flop at that moment; means responsive to said additional control signals to reset said flip-flops; sensing means responsive to a particular signal level stored in a latch circuit indicating that the associated flip-flop has been set; limit selection means for connecting said sensing means to the output of a particular one of said latch circuits thereby selecting the engine speed range at or above which said sensing means is operative to generate said limit signal.
Claim 21
Dependent Claim
85 words
A timing computer as defined in claim 13 wherein said limit logic comprises multistate means coupled to said engine speed computer, and operative to assume a predetermined one of its states in correspondence to the computed RPM falling within one of a succession of incremental ranges; limit selection means for establishing one of said states as corresponding to an excessive engine speed; means for sensing when said selected state has been reached, and operative thereupon to generate said limit signal for inhibiting said angle readout.
Claim 22
Dependent Claim
91 words
A timing computer as defined in claim 13 further including angle range computation means comprising means for selecting target and tolerance values for the timing angle; means for comparing the count in said main counter with the range established by said target and tolerance values, and logic means to generate a first signal indicative that said acTual count exceeds the maximum acceptable value, a second signal indicating that said actual count is within the selected tolerance range, and a third signal indicating that said count is below said lower tolerance limits.
Claim 23
Dependent Claim
188 words
A timing computer as defined in claim 18 wherein said angle range computing means comprises first and second computation counters; means to enter a count in said first and second counters corresponding to the selected target angle; means to increase the count in said first counter by a count equal to the selected tolerance, means to decrease the count in the second counter by a number of counts corresponding to the selected tolerance; a first comparator coupled to said main counter and to said first computation counter; a second comparator coupled to said main counter and to said second computation counter; and logic means coupled to said first and second comparators to provide said first indication if the count in said main counter exceeds that in the first computation counter, to provide said second indication if the count in said main counter is less than or equal to the count in said first computation counter and is greater than or equal to the count in said second computation counter, and said third indication if the count in said main counter is less than that in second computation counter.
Claim 24
Dependent Claim
57 words
A timing computer as defined in claim 19 further including means to preset said main counter and said first and second computation counters to a reference count such that the total count in said second computation counter, including said reference count plus the difference between said target count and said tolerance count, does not fall below zero.
Claim 25
Dependent Claim
367 words
An averaging computer for an internal combustion engine timing apparatus, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; said averaging computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an igntion pulse and referencepulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter, said coupling means comprising frequency division means having a division base N; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; and control means for said averaging computer, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of a total of N timing intervals to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means; said number N being in excess of the number of cyclinders in the engine being timed; whereby the count transferred to said storage means represents the average number of fractional parts of an engine revolution contained in the previously measured N timing intervals.
Claim 26
Dependent Claim
367 words
An averaging computer for an internal combustion engine timing apparatus, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; said averaging computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an igntion pulse and referencepulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter, said coupling means comprising frequency division means having a division base N; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; and control means for said averaging computer, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of a total of N timing intervals to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means; said number N being in excess of the number of cyclinders in the engine being timed; whereby the count transferred to said storage means represents the average number of fractional parts of an engine revolution contained in the previously measured N timing intervals.
Claim 27
Dependent Claim
26 words
A timiNg computer as defined in claim 21 wherein said number N is an integral multiple of the number of cylinders in the engine being timed.
Claim 28
Dependent Claim
56 words
A timing computer as defined in claim 21 wherein said control means includes calibrating means responsive to passage of a predetermined number of timing interals to reduce the count stored in said main counter by a number corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston.
Claim 29
Dependent Claim
55 words
A timing computer as defined in claim 21 further including engine speed computing means; limit logic to establish a maximum acceptable engine speed; means responsive to the sensing of an engine speed exceeding the preset limit to generate a limit signal; and means responsive to said limit signal to disable said timing angle readout unit.
Claim 30
Dependent Claim
85 words
A timing computer as defined in claim 24 wherein said limit logic comprises multistate means coupled to said engine speed computer, and operative to assume a predetermined one of its states in correspondence to the computed RPM falling within one of a succession of incremental ranges; limit selection means for establishing one of said states as corresponding to an excessive engine speed; means for sensing when said selected state has been reached, and operative thereupon to generate said limit signal for inhibiting said angle readout.
Claim 31
Dependent Claim
91 words
A timing computer as defined in claim 21 further including angle range computation means comprising means for selecting target and tolerance values for the timing angle; means for comparing the count in said main counter with the range established by said target and tolerance values, and logic means to generate a first signal indicative that said actual count exceeds the maximum acceptable value, a second signal indicating that said actual count is within the selected tolerance range, and a third signal indicating that said count is below said lower tolerance limits.
Claim 32
Dependent Claim
120 words
A timing computer as defined in claim 21 wherein said means for establishing said timing interval comprises selection means for establishing retard and advance modes of operation; a set-reset flip-flop; logic means responsive to selection of the advance mode of operation for coupling the ignition pulses to the set input of said flip-flop, and the reference pulses to the reset input of said flip-flop, said logic means further being responsive to selection of the retard mode for coupling the reference pulse to the set input of said flip-flop, and the ignition pulses to the reset input of said flip-flop; means for coupling one output of said flip-flop to said gating means to actuate the same when said flip-flop is set.
Claim 33
Dependent Claim
138 words
A timing computer as defined in claim 27 wherein said interval counting means comprises an N-bit counter; means responsive to transition of said set-reset flip-flop to its reset condition to increase the count in said N-bit counter by one bit; means responsive to said interval counter reaching a count of N to generate said control signal; a third counter, means for coupling said master pulse train to operate said third counter; means coupled to said third counter, and responsive to particular count states thereof to generate second and third control signals at predetermined intervals after said first control signal; means for coupling said second control signal to actuate said angle readout storage means; means responsive to said third control signal for resetting said main counter, and means responsive to said first control signal to reset said third counter.
Claim 34
Dependent Claim
178 words
A timing computer as defined in claim 28 further including calibration means responsive to said first control signal, said calibration means comprising a fourth counter; means responsive to said first control signal to establish a calibration interval; gating means coupling said master pulse train to the input of said fourth counter, said gating means being operative during said calibration interval to pass said master pulse train to said fourth counter; means for reducing the count in said main counter in synchronism with the operation of said fourth counter; means responsive to a predetermined count in said fourth counter corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston to terminate said calibration interval; means responsive to termination of said calibration interval to reset said fourth counter, and means responsive to establishment of said calibration interval to prevent operation of said set-reset flip-flop, thereby preventing establishment of intervals for said main counter during said calibration interval, and further means to prevent operation of said third counter during said calibration interval.
Claim 35
Dependent Claim
195 words
A timing computer as defined in claim 21 further including engine speed computing means comprising an engine speed counter; frequency division means coupling said master pulse train to operate said engine speed counter; engine speed readout means comprising means for storing a count contained in said engine speed counter, and visual display means for said stored count; clock means for producing a periodic signal defining an engine speed computation interval; means responsive to the end of a computation cycle to generate a further control signal; means responsive to said further control signal for operating said storage means to store the count then contained in said engine speed counter; means responsive to said further control signal to generate an additional control signal a predetermined time thereafter; and means responsive to said additional control signal to reset said engine speed counter, the counting base of said frequency divider and the duration of said computing interval being so selected in relation to the number of master pulses per engine revolution that the count contained in said speed counter at the end of the computation interval is equal to the average engine speed in RPM during the computing interval.
Claim 36
Dependent Claim
219 words
A timing computer as defined in claim 30 further including a limit logic for establishing a maximum acceptable engine speed, comprising first circuit means coupled to said engine speed counter, a plurality of set-reset flip-flops, said first circuit means being operative to set said flip-flops in a predetermined order as the count in said speed counter increases by predetermined increments whereby, at the end of said computation interval one or more flip-flops are set indicating the number of incremental advances of said engine speed counter during said computation interval; latching means having individual latch circuits connected to the outputs of respective ones of said flip-flops; said latch circuits being responsive to said further control signal to store respective signals indicative of the state of the associated flip-flop at that moment; means responsive to said additional control signals to reset said flip-flops; sensing means responsive to a particular signal level stored in a latch circuit indicating that the associated flip-flop has been set to generate a limit signal; selection means for connecting said sensing means to the output of a particular one of said latch circuits thereby selecting the engine speed range at or above which said sensing means is operative to generate said limit signal; and means responsive to said limit signal to disable said timing angle readout unit.
Claim 37
Dependent Claim
190 words
A timing computer as defined in claim 21 further including angle range computing means comprising first and second computation counters; means to enter a count in said first and second counters corresponding to a selected target timing angle; means to increase the count in said first counter by a count equal to a selected tolerance angle; means to decrease the count in the second counter by a number of counts corresponding to the selected tolerance; a first comparator coupled to said main counter and to said first computator counter; a second comparator coupled to said main counter and to said second compuation counter; and lOgic means coupled to said first and second comparators to provide a first indication if the count in said main counter exceeds that in the first computation counter, to provide a second indication if the count in said main counter is less than or equal to the count in said first computation counter and is greater than or equal to the count in said second computation counter, and a third indication if the count in said main counter is less than that in second computation counter.
Claim 38
Dependent Claim
57 words
A timing computer as defined in claim 32 further including means to preset said main counter and said first and second computation counters to a reference count such that the total count in said second computation counter, including said reference count plus the difference between said target count and said tolerance count, does not fall below zero.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-22 | 1977-04-23 | 1977-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-22 | 1981-04-23 | 1981-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-22 | 1985-04-23 | 1985-10-23 | $7700.00 | Window Closed / Lapsed |