Heterojunction field effect device having an implanted region within a device channel

Claim 2

A semiconductor device comprising: a semiconductor substrate; a first semiconductor layer having an n-type conductivity, formed over said semiconductor substrate, and including first and second layers; a second semiconductor layer, formed between said semiconductor substrate and said first semiconductor layer, said second semiconductor layer being undoped and having an electron affinity greater than that of said first semiconductor layer, said second semiconductor layer being formed in contact with said first layer of said first semiconductor layer and a heterojunction being formed therebetween, to allow a two-dimensional electron gas to accumulate in said second semiconductor layer along said heterojunction, said two-dimensional electron gas providing a current path; an n-type region formed in a surface portion of said second semiconductor layer and directly contacting said first layer of said first semiconductor layer so as to contact said two-dimensional electron gas, said n-type region having first and second ends and formed in a portion of said current path, said first and second ends of said n-type region contacting said two-dimensional electron gas; a source region and a drain region formed in said first semiconductor layer and extending into said second semiconductor layer, said source and drain regions formed in said second semiconductor layer at predetermined lateral distances from said n-type region; a source electrode and a drain electrode formed on said second layer of said first semiconductor layer and ohmically contacting said two-dimensional electron gas; and a gate electrode formed on said second layer of said first semiconductor layer between said source and drain electrodes and directly above said n-type region.

Claim 3

A semiconductor device comprising: a semiconductor substrate; an enhancement mode element formed on said semiconductor substrate, said enhancement mode element including: a first semiconductor layer having an n-type conductivity and having a first ion-implanted portion; a second semiconductor layer, formed on said semiconductor substrate and being undoped, having an electron affinity greater than that of said first semiconductor layer, said first ion-implanted portion of said first semiconductor layer extending into said second semiconductor layer, said second semiconductor layer being formed in contact with said first semiconductor layer, forming a first portion of a heterojunction therebetween, to allow a two-dimensional electron gas to accumulate along said first portion of said heterojunction; a first gate electrode formed on said first semiconductor layer; a first source electrode and a first drain electrode formed on said first semiconductor layer, adjacent to said first gate electrode; and a first isolation region, formed surrounding said enhancement mode element, said first isolation region formed by the first ion-implanted portions of said first and second semiconductor layers to provide a high resistivity; and a depletion mode element formed within said semiconductor substrate, said depletion mode element including: said first semiconductor layer having the n-type conductivity and having a second ion-implanted portion; said second semiconductor layer being undoped, having an electron affinity greater than that of said first semiconductor layer, said second ion-implanted portion of said first semiconductor layer extending into said second semiconductor layer, said second semiconductor layer being formed in contact with said first semiconductor layer, forming a second portion of said heterojunction therebetween, to allow the two-dimensional electron gas to accumulate along said second portion of said heterojunction between said first semiconductor layer and said second semiconductor layer; an n-type region formed in said second semiconductor layer at a lateral distance from said second ion-implanted portion in said second semiconductor layer so as to contact said two-dimensional electron gas; a second gate electrode formed on said first semiconductor layer such that the bottom surface of said second gate electrode faces said n-type region; a second source electrode and a second drain electrode formed on said first semiconductor layer at a predetermined distance from said n-type region, and adjacent to said second gate electrode; and a second isolation region formed surrounding said depletion mode element, said second isolation region formed by said second ion-implanted portions of said first and second semiconductor layers to provide a high resistivity.

Claim 4

A semiconductor device comprising: a semiconductor substrate; an enhancement mode element formed on said semiconductor substrate, said enhancement mode element including: a first semiconductor layer having an n-type conductivity and having a first ion-implanted portion; a second semiconductor layer, formed on said semiconductor substrate and being undoped, having an electron affinity greater than that of said first semiconductor layer, said first ion-implanted portion of said first semiconductor layer extending into said second semiconductor layer, said second semiconductor layer being formed in contact with said first semiconductor layer, forming a first portion of a heterojunction therebetween, to allow a two-dimensional electron gas to accumulate along said first portion of said heterojunction; a first gate electrode formed on said first semiconductor layer; a first source electrode and a first drain electrode formed on said first semiconductor layer, adjacent to said first gate electrode; and a first isolation region, formed surrounding said enhancement mode element, said first isolation region formed by the first ion-implanted portions of said first and second semiconductor layers to provide a high resistivity; and a depletion mode element formed within said semiconductor substrate, said depletion mode element including: said first semiconductor layer having the n-type conductivity and having a second ion-implanted portion; said second semiconductor layer being undoped, having an electron affinity greater than that of said first semiconductor layer, said second ion-implanted portion of said first semiconductor layer extending into said second semiconductor layer, said second semiconductor layer being formed in contact with said first semiconductor layer, forming a second portion of said heterojunction therebetween, to allow the two-dimensional electron gas to accumulate along said second portion of said heterojunction between said first semiconductor layer and said second semiconductor layer; an n-type region formed in said second semiconductor layer at a lateral distance from said second ion-implanted portion in said second semiconductor layer so as to contact said two-dimensional electron gas; a second gate electrode formed on said first semiconductor layer such that the bottom surface of said second gate electrode faces said n-type region; a second source electrode and a second drain electrode formed on said first semiconductor layer at a predetermined distance from said n-type region, and adjacent to said second gate electrode; and a second isolation region formed surrounding said depletion mode element, said second isolation region formed by said second ion-implanted portions of said first and second semiconductor layers to provide a high resistivity.

Claim 5

A load element of a semiconductor device comprising: a semiconductor substrate; a first semiconductor layer, formed over said semiconductor substrate and having an n-type conductivity, which acts as an electron source; a second semiconductor layer, formed between said semiconductor substrate and said first semiconductor layer, being undoped and having an electron affinity greater than that of said first semiconductor layer, said second semiconductor layer being formed in contact with said first semiconductor layer, forming a heterojunction therebetween, to allow a two-dimensional electron gas to accumulate in said second semiconductor layer along said heterojunction; an n-type implanted region formed in a portion of said second semiconductor layer, directly contacting said first semiconductor layer and in contact with said two-dimensional electron gas; source and drain regions formed in said first semiconductor layer and extending into said second semiconductor layer, said source and drain regions being a predetermined lateral distance from said n-type implanted region; and a pair of electrical terminals formed on said first semiconductor layer on said source and drain regions and ohmically contacting said two-dimensional electron gas, said pair of electrical terminals being placed so that a current path for the load element is defined by said n-type implanted region and said two-dimensional electron gas.

Claim 6

A load element of a semiconductor device comprising: a semiconductor substrate; a first semiconductor layer, formed over said semiconductor substrate and having an n-type conductivity, which acts as an electron source; a second semiconductor layer, formed between said semiconductor substrate and said first semiconductor layer, being undoped and having an electron affinity greater than that of said first semiconductor layer, said second semiconductor layer being formed in contact with said first semiconductor layer, forming a heterojunction therebetween, to allow a two-dimensional electron gas to accumulate in said second semiconductor layer along said heterojunction; an n-type implanted region formed in a portion of said second semiconductor layer, directly contacting said first semiconductor layer and in contact with said two-dimensional electron gas; source and drain regions formed in said first semiconductor layer and extending into said second semiconductor layer, said source and drain regions being a predetermined lateral distance from said n-type implanted region; and a pair of electrical terminals formed on said first semiconductor layer on said source and drain regions and ohmically contacting said two-dimensional electron gas, said pair of electrical terminals being placed so that a current path for the load element is defined by said n-type implanted region and said two-dimensional electron gas.

Claim 7

A semiconductor device comprising: a substrate; a first semiconductor layer having a first electron affinity and having ion-implanted portions; a second semiconductor layer, having a second electron affinity greater than said first electron affinity and having ion-implanted portions formed under said ion-implanted portions of said first semiconductor layer, formed on said substate and in contact with said first semiconductor layer, forming a heterojunction therebetween for accumulating a two-dimensional gas; an n-type region selectively formed in said second semiconductor layer and along said heterojunction; a gate electrode formed on said first semiconductor layer above said n-type region; isolation regions formed from said ion-implanted portions of said first semiconductor layer and extending into said ion-implanted portions of said semiconductor layer for providing a high resistivity; source and drain regions formed in said first semiconductor layer and extending into said second semiconductor layer and formed adjacent to said isolation regions and at predetermined lateral distances from said n-type region; and source and drain electrodes respectively formed on said source and drain regions.

Claim 8

A semiconductor device comprising: a substrate; a first semiconductor layer having a first electron affinity and having ion-implanted portions; a second semiconductor layer, having a second electron affinity greater than said first electron affinity and having ion-implanted portions formed under said ion-implanted portions of said first semiconductor layer, formed on said substate and in contact with said first semiconductor layer, forming a heterojunction therebetween for accumulating a two-dimensional gas; an n-type region selectively formed in said second semiconductor layer and along said heterojunction; a gate electrode formed on said first semiconductor layer above said n-type region; isolation regions formed from said ion-implanted portions of said first semiconductor layer and extending into said ion-implanted portions of said semiconductor layer for providing a high resistivity; source and drain regions formed in said first semiconductor layer and extending into said second semiconductor layer and formed adjacent to said isolation regions and at predetermined lateral distances from said n-type region; and source and drain electrodes respectively formed on said source and drain regions.

Claim 9

A semiconductor device having a substrate, comprising: a first semiconductor layer having a first electron affinity and having ion-implanted portions; a second semiconductor layer, having a second electron affinity greater than said first electron affinity and having ion-implanted portions, formed on the substrate and in contact with said first semiconductor layer, forming a heterojunction therebetween; an n-type region selectively formed in said second semiconductor layer and along said heterojunction; a gate electrode formed on said first semiconductor layer and above said n-type region; isolation regions formed by said ion-implanted portions of said first semiconductor layer and extending into said ion-implanted portions of said second semiconductor layer; source and drain regions formed adjacent to said isolation regions and at predetermined lateral distances from said n-type region; and source and drain electrode formed on said source and drain regions, respectively.

Claim 10

A semiconductor device having a substrate, comprising: a first semiconductor layer having a first electron affinity and having ion-implanted portions; a second semiconductor layer, having a second electron affinity greater than said first electron affinity and having ion-implanted portions, formed on the substrate and in contact with said first semiconductor layer, forming a heterojunction therebetween; an n-type region selectively formed in said second semiconductor layer and along said heterojunction; a gate electrode formed on said first semiconductor layer and above said n-type region; isolation regions formed by said ion-implanted portions of said first semiconductor layer and extending into said ion-implanted portions of said second semiconductor layer; source and drain regions formed adjacent to said isolation regions and at predetermined lateral distances from said n-type region; and source and drain electrode formed on said source and drain regions, respectively.