Method of making a silicon nitride resistor using plasma enhanced chemical vapor deposition

Claim 1

A process for fabricating a silicon-rich silicon nitride integrated circuit resistor comprising the steps of: growing a gate-oxide layer on a substrate; removing a portion of said gate-oxide layer to expose said substrate; forming a polysilicon layer on said gate-oxide and said portion of exposed substrate; doping said polysilicon layer by phosphorus diffusion wherein a buried contact region is formed in said portion of exposed substrate; forming a layer of tungsten-silicon on said polysilicon layer; growing an oxide layer on said tungsten-silicon layer; forming an insulative layer on said oxide layer; opening a window in said insulative layer and said oxide, wherein said opening extends to said tungsten-silicon layer; forming a film of silicon-rich silicon nitride in said window, said silicon-rich silicon nitride film being deposited in said window using a plasma enhanced chemical vapor deposition technique at approximately 500 degrees C., said silicon-rich silicon nitride film contacting said tungstensilicon layer; annealing said silicon-rich silicon nitride film at temperatures above 600 degrees C. wherein said annealing temperature and cycle times determine resistivity of said film; forming a barrier layer comprised of titanium nitride on said annealed silicon-rich silicon nitride film; forming a second conductive layer on said barrier layer, said second conductive layer having a titanium layer and an aluminum-silicon layer; whereby a resistor element is fabricated between two conductors in an integrated circuit.