Patent US4737828A successfully refreshed from Google Patents.
US4737828A
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US
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Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom
Assignee: Intersil Corp
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Filing: 1986-03-17
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Granted: 1988-04-12
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Expires: 2006-03-17
Abstract
Abstract An edge defining method is employed in the fabrication of narrow electrical patterns for VLSI circuits. The method is particularly employable in the formation of inlay MOSFET transistors having extremely narrow gate widths. The method is also particularly amenable to the fabrication of both symmetrical and non-symmetrical MOSFET devices on the same VLSI circuit chip. The inlay transistor structure is also employed to fabricate NOR and NAND type "ladder" networks and to join vertically and horizontally adjacent semiconductor devices.
Inventors
- 👤 Dale M. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:30
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0221; H10D30/60; H10D30/601; H10D30/608; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
67 words
A method for forming narrow electrically conductive circuit patterns, said method comprising: disposing an electrically conductive material on the sidewall of a depository layer said depository layer being disposed on top of an insulative substrate and said depository layer also having a protective layer disposed on the top thereof so as to make the disposition of said conductive material selective to the sidewall of said depository layer.
Claim 2
Independent Claim
67 words
A method for forming narrow electrically conductive circuit patterns, said method comprising: disposing an electrically conductive material on the sidewall of a depository layer said depository layer being disposed on top of an insulative substrate and said depository layer also having a protective layer disposed on the top thereof so as to make the disposition of said conductive material selective to the sidewall of said depository layer.
Claim 3
Dependent Claim
12 words
The method of claim 1 in which said depository material comprises metal.
Claim 4
Dependent Claim
23 words
The method of claim 2 in which said protective layer comprises material selected from the group consisting of silicon oxide and silicon nitride.
Claim 5
Dependent Claim
37 words
The method of claim 2 in which said depository layer comprises material selected from the group consisting of tungsten and molybdenum and in which said electrically conductive material is distinct from the material of said depository layer.
Claim 6
Dependent Claim
18 words
The method of claim 2 in which said electrically conductive material is disposed by selective chemical vapor deposition.
Claim 7
Dependent Claim
12 words
The method of claim 1 in which said depository layer comprises polysilicon.
Claim 8
Dependent Claim
23 words
The method of claim 6 in which said protective layer comprises material selected from the group consisting of silicon oxide and silicon nitride.
Claim 9
Dependent Claim
21 words
The method of claim 6 in which said electrically conductive material is disposed on said sidewall by selective chemical vapor deposition.
Claim 10
Dependent Claim
21 words
The method of claim 8 in which said electrically conductive material is selected from the group consisting of tungsten and molybdenum.
Claim 11
Dependent Claim
21 words
The method of claim 1 in which said depository layer comprises material selected from the group consisting of tungsten and molybdenum.
Claim 12
Dependent Claim
22 words
The method of claim 1 in which said depository layer comprises silicon and said conductive material comprises material produced by silicide formation.
Claim 13
Dependent Claim
17 words
The method of claim 11 in which said silicides include palladium silicide, platinum silicide and tungsten silicide.
Claim 14
Dependent Claim
13 words
The method of claim 1 in which said depository layer comprises silicon nitride.
Claim 15
Dependent Claim
41 words
The method of claim 11 in which said disposing of said electrically conductive material on said sidewall comprises depositing said electrically conductive material and then reactively ion etching said electrically conductive material so as to form an edge defined gate pattern.
Claim 16
Independent Claim
64 words
A method for forming narrow conductive electrical circuit patterns said method comprising, depositing by chemical vapor deposition, a metal pattern on the sidewall of a depository layer, said depository layer being disposed on top of at least one insulative area overlying a semiconductor material, said depository layer also having a protective layer disposed thereon so that said metal deposition is selective to said sidewall.
Claim 17
Independent Claim
64 words
A method for forming narrow conductive electrical circuit patterns said method comprising, depositing by chemical vapor deposition, a metal pattern on the sidewall of a depository layer, said depository layer being disposed on top of at least one insulative area overlying a semiconductor material, said depository layer also having a protective layer disposed thereon so that said metal deposition is selective to said sidewall.
Claim 18
Dependent Claim
22 words
The method of claim 15 in which said depository layer comprises material selected from the group consisting of polysilicon, molybdenum and tungsten.
Claim 19
Independent Claim
144 words
A method for forming a gate electrode in a transistor, said method comprising: forming an active region in a semiconductor material, said region being characterized in that it is substantially electrically isolated from the rest of said semiconductor material and disposed in a recess in insulative material which provides said electrical isolation; forming a layer of gate insulation material over said active area in said recess; disposing a depository layer over said gate insulation material; removing a portion of said depository layer so as to define a substantially vertical sidewall edge extending across at least a portion of said active area; forming a gate electrode layer on said sidewall edge, said gate layer comprising a material which is distinct from said depository layer; and selectively removing said depository layer, whereby a narrow gate electrode remains disposed over said gate insulation layer in said recess.
Claim 20
Independent Claim
144 words
A method for forming a gate electrode in a transistor, said method comprising: forming an active region in a semiconductor material, said region being characterized in that it is substantially electrically isolated from the rest of said semiconductor material and disposed in a recess in insulative material which provides said electrical isolation; forming a layer of gate insulation material over said active area in said recess; disposing a depository layer over said gate insulation material; removing a portion of said depository layer so as to define a substantially vertical sidewall edge extending across at least a portion of said active area; forming a gate electrode layer on said sidewall edge, said gate layer comprising a material which is distinct from said depository layer; and selectively removing said depository layer, whereby a narrow gate electrode remains disposed over said gate insulation layer in said recess.
Claim 21
Dependent Claim
32 words
The method of claim 17 further including a step of depositing a protective layer over said depository layer and removing said protective layer in conjunction with the removal of said depository layer.
Claim 22
Independent Claim
23 words
The method of claim l7 in which said protective layer comprises material selected from the group consisting of silicon nitride and silicon oxide.
Claim 23
Dependent Claim
28 words
The method of claim 17 further including selective doping of semiconductor material through exposed gate insulation in said active area prior to selective removal of said depository layer.
Claim 24
Dependent Claim
23 words
The method of claim 17 in which said depository layer comprises material selected from the group consisting of metals, polysilicon and silicon nitride.
Claim 25
Dependent Claim
91 words
A transistor comprising: an insulative layer having a recess with a substantially planar floor disposed therein; an active region disposed in said recess as part of said floor, said active area comprising suitably doped semiconductor material, said active region having an area smaller than the total floor area of said recess; and a gate electrode extending across at least a portion of said active region and being insulated therefrom; said active region further including spaced apart and suitably doped source and drain regions disposed on opposite sides of said gate electrode.
Claim 26
Dependent Claim
91 words
A transistor comprising: an insulative layer having a recess with a substantially planar floor disposed therein; an active region disposed in said recess as part of said floor, said active area comprising suitably doped semiconductor material, said active region having an area smaller than the total floor area of said recess; and a gate electrode extending across at least a portion of said active region and being insulated therefrom; said active region further including spaced apart and suitably doped source and drain regions disposed on opposite sides of said gate electrode.
Claim 27
Dependent Claim
24 words
The transistor of claim 22 further including source and drain contacts in electrical contact with said source and drain regions of said semiconductor material.
Claim 28
Dependent Claim
28 words
The transistor of claim 22 in which the area of said active region is substantially less than the total floor area of said recess in said insulative layer.
Claim 29
Dependent Claim
18 words
The transistor of claim 22 in which said recess and said active region are substantially rectangular in shape.
Claim 30
Dependent Claim
18 words
The transistor of claim 22 in which said gate electrode extends entirely across the floor of said recess.
Claim 31
Dependent Claim
13 words
The transistor of claim 22 in which said insulative layer comprises silicon oxide.
Claim 32
Dependent Claim
12 words
The transistor of claim 22 in which said semiconductor material comprises silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-12 | 1991-10-12 | 1992-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-12 | 1995-10-12 | 1996-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-12 | 1999-10-12 | 2000-04-12 | $7700.00 | Window Closed / Lapsed |