Semiconductor memory cell

Claim 2

A semiconductor memory cell comprising: a bit line for writing data; a word line for writing data; a bit line for reading out data; a word line for reading out data; a MOS transistor for writing data, one terminal of the drain-source path of the MOS transistor being connected to said bit line for writing data, and the gate electrode of the MOS transistor being connected to said word line for writing data; a capacitor for storing charges, one electrode of the capacitor being connected to the other terminal of the drain-source path of the MOS transistor; and a MOS transistor for reading out data, one terminal of the drain-source path of the MOS transistor being connected to said bit line for reading out data, the other terminal of the drain-source path of the MOS transistor being connected to said word line for reading out data, and the gate electrode of the MOS transistor being connected to the other electrode of said capacitor.

Claim 3

A semiconductor memory cell according to claim 1, wherein said bit line for writing data and said bit line for reading out data are common.

Claim 4

A semiconductor memory cell according to claim 1, wherein said MOS transistor for writing data and said MOS transistor for reading out data are formed by MOS transistor.

Claim 5

A semiconductor memory cell according to claim 1, wherein said bit line for reading out data is shared by two memory cells.

Claim 6

A semiconductor memory cell according to claim 1, wherein said MOS transistor for reading out data is made of polysilicon formed on a semiconductor substrate.

Claim 7

A semiconducdor memory cell according to claim 5, wherein said gate of said MOS transistor for reading out data is provided in said semiconductor substrate.

Claim 8

A semiconductor memory cell according to claim 5, wherein said gate of said MOS transistor for reading out data is provided on said semiconductor substrate.

Claim 9

A semiconductor memory cell according to claim 1, wherein a dielectric film of said capacitor is formed of a polysilicon film provided in said semiconductor substrate.

Claim 10

A semiconductor memory cell according to claim 1, wherein said word line for writing data and said word line for reading out data are crossed with an insulation film therebetween.

Claim 11

A semiconductor memory cell according to claim 1, wherein a part of said bit lines and said word lines is made of metal.

Claim 12

A semiconductor memory cell according to claim 1, wherein a part of said bit lines and said word lines is made of metal silicide.

Claim 13

A semiconductor memory cell according to claim 1, wherein said bit line for writing data and said bit line for reading out data are connected together.

Claim 14

A semiconductor memory cell according to claim 1, in which said gate electrode of said MOS transistor for reading out data is formed on a semiconductor substrate, and said bit line and word line for reading out data are made of polysilicon.

Claim 15

A semiconductor memory cell according to claim 1, in which said gate electrode of said MOS transistor for reading out data is formed on a semiconductor substrate, and said bit line and word line for reading out data are made of single crystal silicon.

Claim 16

A semiconductor memory cell according to claim 1, wherein said capacitor is a trenched capacitor formed on a semiconductor substrate, and said MOS transistor for reading out data has a polysilicon layer formed on said trenched capacitor, the gate electrode of said MOS transistor for reading out data being formed by an electrode of said trenched capacitor.

Claim 17

A semiconductor memory cell according to claim 1, wherein said capacitor is a trenched capacitor formed on a semiconductor substrate, and said MOS transistor for reading out data has a single crystal layer formed on said trenched capacitor, the gate electrode of said MOS transistor for reading out data being formed by an electrode of said trenched capacitor.

Claim 18

A semiconductor memory cell comprising: a bit line for writing data and reading out data; a word line for writing data; a word line for reading out data; a MOS transistor for writing data, one terminal of the drain-source path of the MOS transistor being connected to said bit line, and the gate electrode of the MOS transistor being connected to said word line for writing data; a capacitor for storing charges, one electrode of the capacitor being connected to the other terminal of the drain-source path of the MOS transistor, and the other electrode of the capacitor being connected to a predetermined potential; and a MOS transistor for reading out data, one terminal of the drain-source path of the MOS transistor being connected to said bit line, the other terminal of the drain-source path of the MOS transistor being connected to said word line for reading out data, and the gate electrode of the MOS transistor being connected to said one electrode of said capacitor.

Claim 19

A semiconductor memory cell comprising: a bit line for writing data and reading out data; a word line for writing data; a word line for reading out data; a MOS transistor for writing data, one terminal of the drain-source path of the MOS transistor being connected to said bit line, and the gate electrode of the MOS transistor being connected to said word line for writing data; a capacitor for storing charges, one electrode of the capacitor being connected to the other terminal of the drain-source path of the MOS transistor, and the other electrode of the capacitor being connected to a predetermined potential; and a MOS transistor for reading out data, one terminal of the drain-source path of the MOS transistor being connected to said bit line, the other terminal of the drain-source path of the MOS transistor being connected to said word line for reading out data, and the gate electrode of the MOS transistor being connected to said one electrode of said capacitor.

Claim 20

A semiconductor memory cell according to claim 17, in which said capacitor is a trenched capacitor formed on a semiconductor substrate, and said MOS transistor for reading out data has a polysilicon layer formed on said trenched capacitor.