Tape automated manufacture of power semiconductor devices

Claim 2

A process for manufacturing a power semiconductor device comprising the steps of: (a) providing a metal tape carrier including a series of sprocket holes adapted to be engaged by a drive mechanism for automated movement of said tape carrier; (b) providing a plate-shaped power chip having a first main current electrode on a first major chip surface and a second main current electrode and at least one control electrode on a second major chip surface, respectively; (c) bonding said second main current electrode to a major surface of said metal tape carrier; and (d) forming a control lead for contact with said control electrode, said control lead being formed from said tape carrier by severing and electrically isolating an elongated portion of said carrier from the remainder of said carrier.

Claim 3

The power semiconductor device manufacturing process of claim 1 further including the feature of electrical testing of said semiconductor chip, comprising the steps of: (a) pressing a first electrical contact against said first main electrode, a second electrical contact against said control lead and a third electrical contact against said tape carrier; and (b) testing said power semiconductor chip by monitoring electrical conditions intermediate said contacts.

Claim 4

The power semiconductor device manufacturing process of claim 2 further comprising the step of: providing on said tape carrier indicia recording a result of said step of electrically testing said chip.

Claim 5

The power semiconductor device manufacturing process of claim 1 further comprising the step of: configuring said second control lead into a desired shape for use in a semiconductor package.

Claim 6

The power semiconductor device manufacturing process of claim 1 wherein the step of providing a metal tape carrier includes providing a metal tape carrier comprising a metal central portion having a thermal expansion coefficient no greater than about twice that of said power semiconductor chip.

Claim 7

The power semiconductor device manufacturing process of claim 5 wherein the step of providing a metal tape carrier further comprises providing a respective, relatively-higher electrical conductivity metal layer on each major side of said metal central portion.

Claim 8

A process for manufacturing a power semiconductor device comprising the steps of: (a) providing a metal tape carrier including a series of sprocket holes adapted to be engaged by a drive mechanism for automated movement of said tape carrier; (b) providing a plate-shaped power semiconductor chip including a first main current electrode on a first major chip surface and a second main current electrode and at least one control electrode on a second major chip surface; (c) forming a control lead in said tape carrier by removing selected portions of said tape carrier to define part of the lateral periphery of said control lead with at least one selected portion of the control lead lateral periphery remaining intact so as to anchor the control lead to the remainder of said tape carrier; (d) bonding said second main current electrode and said control electrode to a main current section of said tape carrier and to said control lead, respectively; (e) removing said selected portion of said control lead lateral periphery so as to electrically isolate said control lead from the remainder of said tape carrier; and (f) forming a second main current lead from said metal tape by severing from said tape said main current section of said tape carrier and at least one extension thereof.

Claim 9

A process for manufacturing a power semiconductor device comprising the steps of: (a) providing a metal tape carrier including a series of sprocket holes adapted to be engaged by a drive mechanism for automated movement of said tape carrier; (b) providing a plate-shaped power semiconductor chip including a first main current electrode on a first major chip surface and a second main current electrode and at least one control electrode on a second major chip surface; (c) forming a control lead in said tape carrier by removing selected portions of said tape carrier to define part of the lateral periphery of said control lead with at least one selected portion of the control lead lateral periphery remaining intact so as to anchor the control lead to the remainder of said tape carrier; (d) bonding said second main current electrode and said control electrode to a main current section of said tape carrier and to said control lead, respectively; (e) removing said selected portion of said control lead lateral periphery so as to electrically isolate said control lead from the remainder of said tape carrier; and (f) forming a second main current lead from said metal tape by severing from said tape said main current section of said tape carrier and at least one extension thereof.

Claim 10

The power semiconductor device manufacturing process of claim 7 further including the feature of electrical testing of said semiconductor chip, comprising the steps of: (a) pressing a minimum of a pair of opposing main electrical contacts against said first main electrode and said main current section of said tape carrier, respectively, the main electrical contact pressed against said first main electrode constituting a heat sink for removal of heat from said power semiconductor chip; and (b) electrically testing said power semiconductor chip.

Claim 11

The power semiconductor device manufacturing process of claim 8 further comprising, prior to the step of severing said selected portion of the control lead lateral periphery, the step of: dielectrically supporting said control lead in a substantially fixed relation to the remainder of said tape carrier.

Claim 12

The power semiconductor device manufacturing process of claim 7 further comprising, prior to the step of severing said selected portion of the control lead lateral periphery, the step of: dielectrically supporting said control lead in a substantially fixed relation to the remainder of said tape carrier.

Claim 13

The power semiconductor device manufacturing process of claim 7 further comprising the step of: configuring said second main current lead and said control lead into respective, desired shapes for use in a semiconductor package.

Claim 14

The power semiconductor device manufacturing process of claim 7 wherein the step of providing a metal tape carrier includes providing a metal tape carrier comprising a metal central portion having a thermal expansion coefficient no greater than about twice that of said power semiconductor chip.

Claim 15

The power semiconductor device manufacturing process of claim 12 wherein the step of providing a metal tape carrier further comprises providing a respective, relatively-higher electrical conductivity metal layer on each major side of said metal central portion.