Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said address circuit includes a principal portion constructed of a first CMOS circuit, and at least a first bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said address circuit, and wherein said signal circuit includes an input circuit which supplies a data signal to a data line coupled to at least said specified memory cell, said input circuit including a principal portion constructed of a second CMOS circuit and at least a second bipolar output transistor, which executes at least one of charge and discharge of said data line.

Claim 3

A semiconductor integrated circuit as defined in claim 1, wherein said address circuit further includes a third bipolar output transistor which executes the other of charge and discharge of said signal output line, and wherein said input circuit of said signal circuit further includes a fourth biplar output transistor which executes the other of charge and discharge of said data line.

Claim 4

A semiconductor circuit as defined in claim 1, wherein said signal circuit includes a data output buffer for obtaining an information output signal, an input stage of said data output buffer being constructed of a plurality of CMOS circuits, an output stage of said data output buffer including N-channel and P-channel output MISFETs, and wherein said data output buffer further includes a plurality of bipolar output transistors which execute charge and discharge of gate capacitances of said N-channel and P-channel output MISFETs in response to output signals of said plurality of CMOS circuits in said data output buffer.

Claim 5

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said signal circuit includes an input circuit which supplies a data signal to a data line coupled to at least said specified memory cell, said input circuit including a principal portion constructed of a first CMOS circuit and at least a first bipolar output transistor, which executes at least one of charge and discharge of said data line, and wherein said timing circuit includes a principal portion constructed of a second CMOS circuit and at least a second bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said timing circuit.

Claim 6

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said signal circuit includes an input circuit which supplies a data signal to a data line coupled to at least said specified memory cell, said input circuit including a principal portion constructed of a first CMOS circuit and at least a first bipolar output transistor, which executes at least one of charge and discharge of said data line, and wherein said timing circuit includes a principal portion constructed of a second CMOS circuit and at least a second bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said timing circuit.

Claim 7

A semiconductor integrated circuit as defined in claim 4, wherein said input circuit of said signal circuit further includes a third bipolar output transistor which executes the other of charge and discharge of said data line, and wherein said timing circuit further includes a fourth bipolar output transistor which executes the other of charge and discharge of said signal output line.

Claim 8

A semiconductor integrated circuit as defined in claim 4, wherein said signal circuit includes a data output buffer for obtaining an information output signal, an input stage of said data output buffer being constructed of a plurality of CMOS circuits, an output stage of said data output buffer including N-channel and P-channel output MISFETs, and wherein said data output buffer further includes a plurality of bipolar output transistors which execute charge and discharge of gate capacitances of said N-channel and P-channel output MISFETs in response to output signals of said plurality of CMOS circuits in said data output buffer.

Claim 9

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said address circuit includes a principal portion constructed of a first CMOS circuit, and at least a first bipolar output transistor, which executes at least one of charge and discharge of a first signal output line of at least one circuit in said address circuit, and wherein said timing circuit includes a principal portion constructed of a second CMOS circuit and at least a second bipolar output transistor, which executes at least one of charge and discharge of a second output line of at least one circuit in said timing circuit.

Claim 10

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said address circuit includes a principal portion constructed of a first CMOS circuit, and at least a first bipolar output transistor, which executes at least one of charge and discharge of a first signal output line of at least one circuit in said address circuit, and wherein said timing circuit includes a principal portion constructed of a second CMOS circuit and at least a second bipolar output transistor, which executes at least one of charge and discharge of a second output line of at least one circuit in said timing circuit.

Claim 11

A semiconductor integrated circuit as defined in claim 7, wherein said address circuit further includes a third bipolar output transistor which executes the other of charge and discharge of said first signal output line, and wherein said timing circuit further includes a fourth bipolar output transistor which executes the other of charge and discharge of said second signal output line.

Claim 12

A semiconductor integrated circuit as defined in claim 7, wherein said signal circuit includes a data output buffer for obtaining an information output signal, an input stage of said data output buffer eing constructed of a plurality of CMOS circuits, an output stage of said data output buffer including N-channel and P-channel output MISFETs, and wherein said data output buffer further includes a plurality of bipolar output transistors which execute charge and discharge of gate capacitances of said N-channel and P-channel output MISFETs in response to output signals of said plurality of CMOS circuits in said data output buffer.

Claim 13

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said address circuit includes a principal portion constructed of a first CMOS circuit, and at least a first bipolar output transistor, which executes at least one of charge and discharge of a first signal output line of at least one circuit in said address circuit, wherein said signal circuit includes an input circuit which supplies a data signal to a data line coupled to said specified memory cell, said input circuit including a principal portion constructed of a second CMOS circuit and at least a second bipolar output transistor, which executes at least one of charge and discharge of said data line, and wherein said timing circuit includes a principal portion constructed of a third CMOS circuit and at least a third bipolar output transistor, which executes at least one of charge and discharge of a second output line of at least one circuit in said timing circuit.

Claim 14

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said address circuit includes a principal portion constructed of a first CMOS circuit, and at least a first bipolar output transistor, which executes at least one of charge and discharge of a first signal output line of at least one circuit in said address circuit, wherein said signal circuit includes an input circuit which supplies a data signal to a data line coupled to said specified memory cell, said input circuit including a principal portion constructed of a second CMOS circuit and at least a second bipolar output transistor, which executes at least one of charge and discharge of said data line, and wherein said timing circuit includes a principal portion constructed of a third CMOS circuit and at least a third bipolar output transistor, which executes at least one of charge and discharge of a second output line of at least one circuit in said timing circuit.

Claim 15

A semiconductor integrated circuit as defined in claim 10, wherein said address circuit further includes a fourth bipolar output transistor which executes the other of charge and discharge of said first signal output line, wherein said input circuit of said signal circuit further includes a fifth bipolar output transistor which executes the other of charge and discharge of said data line, and wherein said timing circuit further includes a sixth bipolar output transistor which executes the other of charge and discharge of said second output line.

Claim 16

A semiconductor integrated circuit as defined in claim 11, wherein said signal circuit includes a data output buffer for obtaining an information output signal, and input stage of said data output buffer being constructed of a plurality of CMOS circuits, an output stage of said data output buffer including N-channel and P-channel output MISFETs, and wherein said data output buffer further includes a plurality of bipolar output transistors which execute charge and discharge of gate capacitances of said N-channel and P-channel output MISFETs in response to output signals of said plurality of CMOS circuits in said data output buffer.