Structure for high breakdown PN diode with relatively high surface doping

Claim 2

A high voltage PN junction comprising: a first semiconductor region of a first conductivity type having a surface; a second semiconductor region of a second conductivity type in said surface; a field plate separated from said surface by a layer of insulation and extending laterally across said surface from the surface junction of said first and second regions over said first region; the impurity concentration of said first region decreasing from said surface having a high impurity concentration region at said surface and extending down along a substantial portion of the depth of said second region greater than the depth of and having a higher charge density than a surface accumulation region and a low impurity region adjacent the bottom of said second region so that said high impurity concentration region under said field plate is depleted by biasing said field plate before a critical field is reached in the portion of said high impurity concentration region under said field plate.

Claim 3

A high voltage PN junction according to claim 1, wherein said impurity concentration profile being such that critical field is reached in said high and low impurity concentration regions substantially simultaneously with said field plate biased.

Claim 4

A high voltage PN junction according to claim 1, wherein said first region has a Gaussian impurity profile.

Claim 5

A high voltage PN junction according to claim 1, wherein said high impurity concentration region is a substantially constant impurity concentration region formed along the surface of a substantially constant impurity concentration low impurity region.

Claim 6

A high voltage PN junction according to claim 1, wherein said second region has a greater depth than said high impurity concentration region.

Claim 7

A high voltage PN junction according to claim 1, wherein said high impurity concentration region has a greater depth than said second region.

Claim 8

A high voltage PN junction according to claim 1, wherein said second region is a body of a lateral insulated gate field effect transistor, said first region is a drain of said transistor, said high impurity concentration region extends from said body substantially to a surface drain contact, said field plate is an extension of the gate of said transistor and including a source region in said body region.

Claim 9

A high voltage PN junction according to claim 1, wherein said first region is the base of a lateral bipolar transistor, said second region is a collector of said transistor, said high impurity concentration region extends at least between said collector and an emitter region in said base region.

Claim 10

A high voltage PN junction according to claim 8, wherein said high impurity concentration region has a greater depth than said collector region.

Claim 11

A high voltage PN junction according to claim 8, wherein said field plate extends from said collector and over a substantial portion of said high impurity concentration region between said collector and emitter regions.

Claim 12

A high voltage PN junction according to claim 1, wherein said second region is a base of a vertical bipolar transistor, said first region is a collector of said transistor, said high impurity concentration region extends from said base substantially to a surface collector contact.

Claim 13

A high voltage PN junction according to claim 11, wherein said high impurity concentration region has a greater depth than said base.

Claim 14

A high voltage PN junction according to claim 11, wherein said base has a greater depth than said high impurity concentration region.

Claim 15

A high voltage PN junction according to claim 1, wherein said second region has a greater impurity concentration than said first region.

Claim 16

A high voltage PN junction according to claim 1, wherein said second region has a greater impurity concentration than said low impurity concentration region of said first region.

Claim 17

A high voltage PN junction according to claim 1, wherein the high voltage PN junction is in an integrated circuit including a lateral insulated gate field effect transistor, said transistor has a body of the same characteristics as said first region, a source and drain region of said second conductivity type spaced in said body and having the same characteristics as said second region and a gate separated from said body by a layer of insulation and extending over the portion of said body which extends between said source and drain regions.

Claim 18

A lateral insulated gate field effect transistor according to claim 16, wherein said high impurity concentration region has a greater depth than said source and drain regions.

Claim 19

A high voltage PN junction according to claim 16, wherein said insulative layer is thicker adjacent to said source and drain regions than in the area between said source and drain regions, said field plate forming a gate over said thinner insulative region and a field plate over said thicker insulative region.

Claim 20

A lateral insulated gate field effect transistor comprising: a drain region of a first conductivity type having a surface and a drain contact region on said surface; a body region of a second conductivity type in said surface; a source region of said first conductivity type in said body region and said surface; a field plate and gate separated from said surface by a layer of insulation and extending laterally from said source region across said body region and across a substantial portion of said drain region between said body and drain contact regions; the impurity concentration of said drain region decreases from said surface having a high impurity concentration region at said surface and extending down along a substantial portion of said body region and a low impurity concentration region adjacent the bottom of said body region so that said high impurity concentration region under said field plate is depleted by biasing said field plate before a critical field is reached in the portion of said high impurity concentration region under said field plate.

Claim 21

A lateral insulated gate field effect transistor comprising: a drain region of a first conductivity type having a surface and a drain contact region on said surface; a body region of a second conductivity type in said surface; a source region of said first conductivity type in said body region and said surface; a field plate and gate separated from said surface by a layer of insulation and extending laterally from said source region across said body region and across a substantial portion of said drain region between said body and drain contact regions; the impurity concentration of said drain region decreases from said surface having a high impurity concentration region at said surface and extending down along a substantial portion of said body region and a low impurity concentration region adjacent the bottom of said body region so that said high impurity concentration region under said field plate is depleted by biasing said field plate before a critical field is reached in the portion of said high impurity concentration region under said field plate.

Claim 22

A lateral insulated gate field effect transistor according to claim 19, wherein said impurity concentration profile being such that critical field is reached in said high and low impurity concentration regions substantially simultaneously with said gate biased.

Claim 23

A lateral insulated gate field effect transistor according to claim 19, wherein said drain region has a Gaussian impurity profile.

Claim 24

A lateral insulated gate field effect transistor according to claim 19, wherein said high impurity concentration region is a substantially constant impurity concentration region formed along the surface of a substantially constant impurity concentration low impurity region.

Claim 25

A lateral insulated gate field effect transistor according to claim 19, wherein said body region has a greater depth than said high impurity concentration region.

Claim 26

A lateral insulated gate field effect transistor according to claim 19, wherein said gate extends over said body region and adjacent portions of said drain region and including a field plate spaced from said gate, separated from said surface by said layer of insulation and extending over said portions of drain region between said body and drain contact regions.

Claim 27

A high voltage lateral bipolar transistor comprising: a base region of a first conductivity type and having a surface; an emitter and collector region of a second conductivity type spaced in said surface; a field plate separated from said surface by a layer of insulation and extending laterally from said collector region across said base region; the impurity concentration of said base region decreases from said surface having a high impurity concentration region at said surface and extending down along a substantial portion of the depth of said emitter and collector regions greater than the depth of and having a higher charge density than a surface accumulation region and a low impurity concentration region adjacent the bottom of said emitter and collector regions so that said high impurity concentration region under said field plate is depleted by biasing said field plate before a critical field is reached in the portion of said high impurity concentration region under said field plate.

Claim 28

A high voltage lateral bipolar transistor comprising: a base region of a first conductivity type and having a surface; an emitter and collector region of a second conductivity type spaced in said surface; a field plate separated from said surface by a layer of insulation and extending laterally from said collector region across said base region; the impurity concentration of said base region decreases from said surface having a high impurity concentration region at said surface and extending down along a substantial portion of the depth of said emitter and collector regions greater than the depth of and having a higher charge density than a surface accumulation region and a low impurity concentration region adjacent the bottom of said emitter and collector regions so that said high impurity concentration region under said field plate is depleted by biasing said field plate before a critical field is reached in the portion of said high impurity concentration region under said field plate.

Claim 29

A high voltage lateral bipolar transistor according to claim 25, wherein said high impurity concentration region has a depth greater than said emitter region.

Claim 30

A high voltage lateral bipolar transistor according to claim 26, wherein said high impurity concentration region has a greater depth than said collector region.

Claim 31

A high voltage lateral bipolar transistor according to claim 26, wherein said collector region has a greater depth than said high impurity concentration region.

Claim 32

A high voltage lateral bipolar transistor according to claim 25, wherein said base region has a Gaussian impurity profile.

Claim 33

A high voltage lateral bipolar transistor according to claim 25, wherein said high impurity concentration region is a substantially constant impurity concentration region formed along the surface of a substantially constant impurity concentration low impurity region.

Claim 34

A high voltage lateral bipolar transistor according to claim 25, wherein said field plate extends from said collector across a substantial portion of said base region between said collector and emitter regions.

Claim 35

A vertical bipolar transistor comprising: a collector region of a first conductivity type, having a surface and a collector contact region in said surface; a base region of a second conductivity type in said surface; an emitter region of said first conductivity type in said surface and base region; a field plate separated from said surface by an insulative layer and extending from said base region across said collector region; the impurity concentration of said collector region decreases from said surface, having a high impurity concentration region at said surface and extending down along a substantial portion of the depth of said base region greater than the depth of and having a higher charge density than a surface accumulation region and a low impurity concentration region adjacent the bottom of said base region so that said high impurity concentration region under said field plate is depleted by biasing said field plate before a critical field is reached in the portion of said high impurity concentration region under said field plate.

Claim 36

A vertical bipolar transistor comprising: a collector region of a first conductivity type, having a surface and a collector contact region in said surface; a base region of a second conductivity type in said surface; an emitter region of said first conductivity type in said surface and base region; a field plate separated from said surface by an insulative layer and extending from said base region across said collector region; the impurity concentration of said collector region decreases from said surface, having a high impurity concentration region at said surface and extending down along a substantial portion of the depth of said base region greater than the depth of and having a higher charge density than a surface accumulation region and a low impurity concentration region adjacent the bottom of said base region so that said high impurity concentration region under said field plate is depleted by biasing said field plate before a critical field is reached in the portion of said high impurity concentration region under said field plate.

Claim 37

A vertical bipolar transistor according to claim 32, wherein said high impurity concentration region has a greater depth than said base region.

Claim 38

A vertical bipolar transistor according to claim 32, wherein said collector region has a Gaussian impurity profile.

Claim 39

A vertical bipolar transistor according to claim 32, wherein said high impurity concentration region is a substantially constant impurity concentration region formed along the surface of a substantially constant impurity concentration low impurity region.

Claim 40

A vertical bipolar transistor according to claim 32, including a base contact having a portion extending over said high impurity concentration region and acting as a field plate and wherein said field plate is spaced from said base contact field plate portion and extends over a substantial portion of said high impurity concentration region between said base and collector contact.

Claim 41

In a dielectrically isolated integrated circuit having semiconductor islands of a first conductivity type separated from and in the surface of a semiconductror support by a dielectric layer, a conductor separated by a top insulative layer from and traversing adjacent portions of the top surface of at least one of said semiconductor islands and said semicoductor support, the improvement comprising: the impurity concentration of said semiconductor island decreasing from said top surface having a high impurity concentration region at said top surface and extending down a substantial portion of the depth of said island and a low impurity concentration region adjacent the bottom of said island so that said high impurity concentration region under said conductor is depleted by biasing said conductor before a critical field is reached in the portion of said high impurity concentration region under said conductor.

Claim 42

In a dielectrically isolated integrated circuit having semiconductor islands of a first conductivity type separated from and in the surface of a semiconductror support by a dielectric layer, a conductor separated by a top insulative layer from and traversing adjacent portions of the top surface of at least one of said semiconductor islands and said semicoductor support, the improvement comprising: the impurity concentration of said semiconductor island decreasing from said top surface having a high impurity concentration region at said top surface and extending down a substantial portion of the depth of said island and a low impurity concentration region adjacent the bottom of said island so that said high impurity concentration region under said conductor is depleted by biasing said conductor before a critical field is reached in the portion of said high impurity concentration region under said conductor.