Patent US4670676A successfully refreshed from Google Patents.
US4670676A
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Reset circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1985-01-15
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Granted: 1987-06-02
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Expires: 2005-01-15
Abstract
Abstract A reset circuit resets an internal circuit (3) included in an electronic apparatus. The internal circuit generates a pulse signal indicating that the internal circuit is in an enabled state. This pulse signal is supplied to an inverter (63) through an integrating circuit comprising a resistor (61) and a capacitor (62), so that the pulse signal in the inverter is inverted in polarity to be supplied to one input terminal of an AND gate as a reset inhibit signal. To the other input terminal of the AND gate is supplied a reset signal generated based on transient phenomena at the time of turning on of the DC power source. If the AND gate is closed by the reset inhibit signal, the internal circuit does not receive the reset signal from the AND gate. Accordingly, the internal circuit in operation will never be reset if the reset signal is supplied thereto.
Inventors
- 👤 Kazuharu Nishitani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:55
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/24
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
163 words
A reset circuit for resetting an internal circuit in an electronic apparatus, comprising: an input terminal for receiving an enabling signal for enabling said internal circuit, reset signal generating means responsive to said enabling signal for applying a reset signal to said internal circuit, said internal circuit including means for generating a pulse when said internal circuit is in an enabled state, determining means including an integrator connected to said internal circuit for integrating directly said pulse to provide an exponential waveform of the pulse itself in response thereto to determine that said internal circuit is in a predetermined enabled state, and in response to said exponential waveform, generating a decision signal, and reset inhibit means connected between an output of said reset signal generating means and a reset signal input of said internal circuit and responsive to said decision signal for inhibiting said reset signal from being supplied to said internal circuit when said internal circuit is in said predetermined enabled state.
Claim 2
Dependent Claim
163 words
A reset circuit for resetting an internal circuit in an electronic apparatus, comprising: an input terminal for receiving an enabling signal for enabling said internal circuit, reset signal generating means responsive to said enabling signal for applying a reset signal to said internal circuit, said internal circuit including means for generating a pulse when said internal circuit is in an enabled state, determining means including an integrator connected to said internal circuit for integrating directly said pulse to provide an exponential waveform of the pulse itself in response thereto to determine that said internal circuit is in a predetermined enabled state, and in response to said exponential waveform, generating a decision signal, and reset inhibit means connected between an output of said reset signal generating means and a reset signal input of said internal circuit and responsive to said decision signal for inhibiting said reset signal from being supplied to said internal circuit when said internal circuit is in said predetermined enabled state.
Claim 3
Dependent Claim
21 words
A reset circuit in accordance with claim 1, wherein a microcomputer is included in said internal circuit of said electronic apparatus.
Claim 4
Dependent Claim
33 words
A reset circuit in accordance with claim 1, wherein said reset inhibit means comprises gate means for inhibiting application of said reset signal from said reset signal generating means to said internal circuit.
Claim 5
Dependent Claim
62 words
A reset circuit in accordance with claim 1, wherein said input terminal comprises a power source input terminal to which a DC power source is applied, and said reset signal generating means comprises means for generating said reset signal based on a transient signal at the time of turning on of said DC power source applied to said power source input terminal.
Claim 6
Dependent Claim
32 words
A reset circuit in accordance with claim 1, wherein said determining means further comprises: means for generating said decision signal if said pulse signal integrated by said integrator has a predetermined level.
Claim 7
Dependent Claim
39 words
A reset circuit in accordance with claim 5, wherein said integrator is set to have a time constant larger than the time constant of a transient signal occurring at the time of turning on of a DC power source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-01 | 1990-12-01 | 1991-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-01 | 1994-12-01 | 1995-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-01 | 1998-12-01 | 1999-06-02 | $7700.00 | Window Closed / Lapsed |