US4438357A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Level sensitive reset circuit for digital logic
Assignee: Baxter International Inc
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Filing: 1982-06-17
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Granted: 1984-03-20
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Expires: 2002-06-17
Abstract
Abstract A circuit is provided for resetting a digital logic circuit, such as a digital counter. A switch 16 provides a first signal when a predetermined condition has occcurred. A flip-flop 24 provides an output reset signal when the flip-flop is in a first state, in response to the first signal. The digital logic circuit to be reset 32 is coupled to the output of the flip-flop 24 for receiving its output reset signal. Feedback means 34, 36, 38 are coupled from the digital logic circuit 32 back to the flip-flop 24 for providing a signal to put the flip-flop into its other state whereby its output reset signal is terminated.
Inventors
- 👤 Michael F. Wicnienski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:52
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/24; H; H03; H03K; H03K17/00; H03K17/22; H03K17/51; H03K17/78; H03K17/795; H03K17/7955; H03K21/00; H03K21/38
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
150 words
A system for resetting a digital logic circuit, which comprises: a switch operable to provide a first signal when a predetermined condition has occurred; a bistable device operable to receive said first signal and to provide an output reset signal when the device is in a first state, in response to said first signal; a digital logic circuit to be reset coupled to the output of the bistable device for receiving the output reset signal; feedback means coupled from said digital logic circuit back to said bistable device for sensing the state of the digital logic circuit and for switching the bistable device into a second state only when said logic circuit is in its reset condition whereby said output reset signal is terminated; whereby a functional output from the digital logic circuit is prevented unless the digital logic circuit is in its reset condition when the system is activated.
Claim 2
Independent Claim
150 words
A system for resetting a digital logic circuit, which comprises: a switch operable to provide a first signal when a predetermined condition has occurred; a bistable device operable to receive said first signal and to provide an output reset signal when the device is in a first state, in response to said first signal; a digital logic circuit to be reset coupled to the output of the bistable device for receiving the output reset signal; feedback means coupled from said digital logic circuit back to said bistable device for sensing the state of the digital logic circuit and for switching the bistable device into a second state only when said logic circuit is in its reset condition whereby said output reset signal is terminated; whereby a functional output from the digital logic circuit is prevented unless the digital logic circuit is in its reset condition when the system is activated.
Claim 3
Dependent Claim
23 words
A circuit as described in claim 1, including means for determining when said predetermined condition has occurred, comprising a diode and an LED.
Claim 4
Dependent Claim
17 words
A circuit as described in claim 2, said switch comprising a transistor optically coupled to said LED.
Claim 5
Dependent Claim
32 words
A circuit as described in claim 1, said bistable device comprising a flip-flop with said switch being coupled to its clock input and said feedback means being coupled to its reset input.
Claim 6
Dependent Claim
14 words
A circuit as described in claim 1, said digital logic circuit comprising a counter.
Claim 7
Dependent Claim
22 words
A circuit as described in claim 1, said feedback means including means for sensing that the digital logic circuit has been reset.
Claim 8
Independent Claim
208 words
A system for resetting a digital logic circuit, which comprises: means for determining when a predetermined condition has occurred; a switch which operates to provide a first signal when said predetermined condition has occurred; said means for determining comprising an LED and said switch comprising a transistor optically coupled to said LED; a bistable device coupled to the output of said switch and operable to provide an output reset signal when the device is in a first state, in response to said first signal, said bistable device comprising flip-flop with said switch being coupled to its clock input; a digital counter to be reset coupled to the output of the flip-flop for receiving the output reset signal; feedback means coupled from said digital counter back to said flip-flop for sensing the state of said counter and for switching the flip-flop into a second state only when said counter is in its reset condition whereby said output reset signal is terminated, said feedback means being coupled to the reset input of said flip-flop; said feedback means including means for sensing that the digital counter has been reset; whereby a functional output from the counter is prevented unless the counter is in its reset condition when the system is activated.
Claim 9
Independent Claim
208 words
A system for resetting a digital logic circuit, which comprises: means for determining when a predetermined condition has occurred; a switch which operates to provide a first signal when said predetermined condition has occurred; said means for determining comprising an LED and said switch comprising a transistor optically coupled to said LED; a bistable device coupled to the output of said switch and operable to provide an output reset signal when the device is in a first state, in response to said first signal, said bistable device comprising flip-flop with said switch being coupled to its clock input; a digital counter to be reset coupled to the output of the flip-flop for receiving the output reset signal; feedback means coupled from said digital counter back to said flip-flop for sensing the state of said counter and for switching the flip-flop into a second state only when said counter is in its reset condition whereby said output reset signal is terminated, said feedback means being coupled to the reset input of said flip-flop; said feedback means including means for sensing that the digital counter has been reset; whereby a functional output from the counter is prevented unless the counter is in its reset condition when the system is activated.
Claim 10
Dependent Claim
30 words
A circuit as described in claim 1, said digital logic circuit comprising a multi-stage counter and said feedback means being coupled to check the upper eight bits of said counter.
Claim 11
Dependent Claim
41 words
A circuit as described in claim 8, said feedback means including a NOR gate with the upper eight bits' outputs being connected to inputs of the NOR gate and the output of the NOR gate being coupled to the bistable device.
Claim 12
Dependent Claim
32 words
A circuit as described in claim 9, said bistable device comprising a flip-flop with said switch being coupled to its clock input and said feedback means being coupled to its reset input.
Claim 13
Independent Claim
174 words
A system for resetting a digital logic circuit, which comprises: a first switch operable to provide a first signal when a first predetermined condition has occurred; a second switch operable to provide a second signal when a second predetermined condition has occurred; means for providing a third signal only when said first and second signals are provided; a bistable device operable to receive said third signal and to provide a reset signal when the device is in a first state; a digital logic circuit to be reset coupled to the output of the bistable device for receiving the reset signal; feedback means coupled from the digital logic circuit back to said bistable device for sensing the state of the digital logic circuit and for switching the bistable device into a second state only when said logic circuit is in its reset condition whereby said reset signal is terminated; whereby a functional output from the digital logic circuit is prevented unless the digital logic circuit is in its reset condition when the system is activated.
Claim 14
Independent Claim
174 words
A system for resetting a digital logic circuit, which comprises: a first switch operable to provide a first signal when a first predetermined condition has occurred; a second switch operable to provide a second signal when a second predetermined condition has occurred; means for providing a third signal only when said first and second signals are provided; a bistable device operable to receive said third signal and to provide a reset signal when the device is in a first state; a digital logic circuit to be reset coupled to the output of the bistable device for receiving the reset signal; feedback means coupled from the digital logic circuit back to said bistable device for sensing the state of the digital logic circuit and for switching the bistable device into a second state only when said logic circuit is in its reset condition whereby said reset signal is terminated; whereby a functional output from the digital logic circuit is prevented unless the digital logic circuit is in its reset condition when the system is activated.
Claim 15
Dependent Claim
29 words
A circuit as described in claim 11, including first means for determining when said first condition has occurred and second means for determining when said second condition has occurred.
Claim 16
Dependent Claim
33 words
A circuit as described in claim 12, said first means and said second means each comprising an LED; said first and second switches being optically coupled to said first and second LEDs, respectively.
Claim 17
Dependent Claim
32 words
A circuit as described in claim 11, said bistable device comprising a flip-flop with said switch being coupled to its clock input and said feedback means being coupled to its reset input.
Claim 18
Dependent Claim
22 words
A circuit as described in claim 11, said feedback means including means for sensing that the digital logic circuit has been reset.
Claim 19
Dependent Claim
156 words
A circuit for resetting a digital logic circuit, which comprises: a first switch operable to provide a first signal when a first predetermined condition has occurred; a second switch operable to provide a second signal when a second predetermined condition has occurred; means for providing a third signal only when said first and second signals are provided; a bistable device operable to receive said third signal and to provide a reset signal when the device is in a first state; a digital logic circuit to be reset coupled to the output of the bistable device for receiving the reset signal; and feedback means coupled from the digital logic circuit back to said bistable device for providing a signal to put the bistable device into a second state whereby said reset signal is terminated; said digital logic circuit comprising a multi-stage counter and said feedback means being coupled to check the upper eight bits of said counter.
Claim 20
Dependent Claim
156 words
A circuit for resetting a digital logic circuit, which comprises: a first switch operable to provide a first signal when a first predetermined condition has occurred; a second switch operable to provide a second signal when a second predetermined condition has occurred; means for providing a third signal only when said first and second signals are provided; a bistable device operable to receive said third signal and to provide a reset signal when the device is in a first state; a digital logic circuit to be reset coupled to the output of the bistable device for receiving the reset signal; and feedback means coupled from the digital logic circuit back to said bistable device for providing a signal to put the bistable device into a second state whereby said reset signal is terminated; said digital logic circuit comprising a multi-stage counter and said feedback means being coupled to check the upper eight bits of said counter.
Claim 21
Dependent Claim
182 words
A circuit for resetting a digital logic circuit, which comprises: a first switch operable to provide a first signal when a first predetermined condition has occurred; a second switch operable to provide a second signal when a second predetermined condition has occurred; means for providing a third signal only when said first and second signals are provided; a bistable device operable to receive said third signal and to provide a reset signal when the device is in a first state; a digital logic circuit to be reset coupled to the output of the bistable device for receiving the reset signal; and feedback means coupled from the digital logic circuit back to said bistable device for providing a signal to put the bistable device into a second state whereby said reset signal is terminated, said feedback means including means for sensing that the digital logic circuit has been reset; said feedback means including a NOR gate with the upper eight bits' outputs being connected to inputs of the NOR gate and the output of the NOR gate being coupled to the bistable device.
Claim 22
Dependent Claim
182 words
A circuit for resetting a digital logic circuit, which comprises: a first switch operable to provide a first signal when a first predetermined condition has occurred; a second switch operable to provide a second signal when a second predetermined condition has occurred; means for providing a third signal only when said first and second signals are provided; a bistable device operable to receive said third signal and to provide a reset signal when the device is in a first state; a digital logic circuit to be reset coupled to the output of the bistable device for receiving the reset signal; and feedback means coupled from the digital logic circuit back to said bistable device for providing a signal to put the bistable device into a second state whereby said reset signal is terminated, said feedback means including means for sensing that the digital logic circuit has been reset; said feedback means including a NOR gate with the upper eight bits' outputs being connected to inputs of the NOR gate and the output of the NOR gate being coupled to the bistable device.
Claim 23
Dependent Claim
32 words
A circuit as described in claim 17, said bistable device comprising a flip-flop with said switch being coupled to its clock input and said feedback means being coupled to its reset input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-20 | 1987-09-19 | 1988-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-20 | 1991-09-19 | 1992-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-20 | 1995-09-19 | 1996-03-20 | $7700.00 | Window Closed / Lapsed |