Data processor using picosquencer to control execution of multi-instruction subroutines in a single fetch cycle

Claim 1

A high speed computer system with special subroutine handling capabilities that include means for executing of subroutines of a a plurality of predefined instructions in a single fetch cycle, the high speed computer system comprises: a first processor means for executing each program instruction in a single fetch cycle; an instruction memory means for communicating program instructions to the first processor means at the beginning of each fetch cycle; a data memory means for communicating data to the first processor means during each fetch cycle; and the first processor means includes: subroutine decode means for decoding a subroutine request from a predefined programmed instruction communicated to the first processor means, a picosequencer means for generating the plurality of predefined instructions from the decoded subroutine request for execution thereby within a single fetch cycle, and means for prefetching a program instruction from the instruction memory means during operation by the first processor means on the data provided by the data memory means according to a previously provided program instruction.