US4027292A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronous data processing system having arithmetic and control units controlled by single-phase clock pulses
Assignee: NEC Corp
•
Filing: 1974-12-27
•
Granted: 1977-05-31
•
Expires: 1994-12-27
Abstract
Abstract A synchronous digital data processing system employing single-phase clock pulses comprises arithmetic and control units which are capable of completing an operation during one clock pulse period. The data processing system includes closed data paths wherein only one stage of a memory circuit capable of the same operation as a master/slave flip-flop is used as a data register in the arithmetic unit and as an address register in the control unit. In either case, during one cycle of a single-phase clock pulse, an input data is set in the memory circuit, and the output of the memory circuit is renewed in response to the input data. The output of the memory circuit is held until it is renewed in the following cycle.
Inventors
- 👤 Kiyokazu Okamoto
- 👤 Masayoshi Isomura
- 👤 Atsuto Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:34
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F9/00; G06F9/06; G06F9/22; G06F9/223
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
311 words
A synchronous data processing system comprising an arithmetic unit and a control unit each of which is controlled by single-phase clock pulses, said arithmetic unit and said control unit being in the form of first and second closed data paths, respectively, wherein said arithmetic unit comprises: first bus lines for transferring data, first register means used as a data register having a single stage for storing data transferred by said first bus lines, and first logic circuits; said first bus lines, said first register means and said first logic circuits being connected in said first closed data path, said first logic circuits being responsive to first control signals to cause the data to be stored in a selected part of said first register means according to the data supplied from said first bus lines during one cycle of a single-phase clock pulse, wherein said control unit comprises: second bus lines for transferring data, second register means used as an address register having a single stage for storing data transferred by said second bus lines, second logic circuits; said second bus lines, said second register means and said second logic circuits being connected in said second closed data path, said second logic circuits being responsive to second control signals to cause data to be stored in said second register means according to the data supplied by said second bus lines during one cycle of a single-phase clock pulse, and control signal generating means connected to receive an output of said second register means for generating said first and second control signals as a predetermined response to coded output data from said second register means, and wherein said second bus lines are connected to said arithmetic unit to form a third closed data path including said second register means and said first logic circuits to exchange data between said arithmetic and control units.
Claim 2
Dependent Claim
311 words
A synchronous data processing system comprising an arithmetic unit and a control unit each of which is controlled by single-phase clock pulses, said arithmetic unit and said control unit being in the form of first and second closed data paths, respectively, wherein said arithmetic unit comprises: first bus lines for transferring data, first register means used as a data register having a single stage for storing data transferred by said first bus lines, and first logic circuits; said first bus lines, said first register means and said first logic circuits being connected in said first closed data path, said first logic circuits being responsive to first control signals to cause the data to be stored in a selected part of said first register means according to the data supplied from said first bus lines during one cycle of a single-phase clock pulse, wherein said control unit comprises: second bus lines for transferring data, second register means used as an address register having a single stage for storing data transferred by said second bus lines, second logic circuits; said second bus lines, said second register means and said second logic circuits being connected in said second closed data path, said second logic circuits being responsive to second control signals to cause data to be stored in said second register means according to the data supplied by said second bus lines during one cycle of a single-phase clock pulse, and control signal generating means connected to receive an output of said second register means for generating said first and second control signals as a predetermined response to coded output data from said second register means, and wherein said second bus lines are connected to said arithmetic unit to form a third closed data path including said second register means and said first logic circuits to exchange data between said arithmetic and control units.
Claim 3
Dependent Claim
199 words
A synchronous data processing system as recited in claim 1, wherein said first logic circuits include arithmetic-logic means having two inputs and one output for performing arithmetic and logic operations on operand data supplied to said two inputs and generating resultant data at said output in response to said first control signals, said first register means having two inputs and two outputs and being responsive to said first control signals, the output of said arithmetic-logic means being connected to said two inputs of said first register means and the two outputs of said first register means being connected to said two inputs of said arithmetic-logic means to form said first closed data path, said first register means being responsive to said first control signals for storing data supplied to its two inputs and emitting the contents of said first register means at its two outputs independently of each other during one cycle of a single-phase clock pulse, one of said outputs of said first register means being adapted to be connected to supply address data to a memory unit with data to and from the memory unit being adapted to be selectively connected to said first closed data path.
Claim 4
Dependent Claim
275 words
A synchronous data processing system as recited in claim 2, wherein said control signal generating means includes a read only memory means having an address input, said read only memory means being responsive to coded output data from said second register means supplied to said address input for generating said first and second control signals, said second logic circuits including address code generating means for generating address codes designating the contents of said second register means to be applied to the address input of said read only memory means in response to said second control signals during one cycle of a single-phase clock pulse, said second register means having two inputs and two outputs for independently storing the data supplied to its two inputs and emitting the contents of said second register means designated by said address codes at its two outputs independently of each other upon application of a single-phase clock pulse, said second logic circuits further including incrementing means having an input and an output for adding one to input data supplied to its input, one of said outputs of said second register means being connected to the address input of said read only memory means and to the input of said incrementing means and the output of said incrementing means being connected to one of the inputs of said second register means to form said second closed data path, and the other output of said second register means being connected to an input of said arithmetic-logic means and the output of said arithmetic-logic means being connected to the other input of said second register means to form said third closed data path.
Claim 5
Dependent Claim
72 words
A synchronous digital data processing system as recited in claim 1 comprising a plurality of said arithmetic and control units adapted to operate independently of each other, individually and in parallel with each other in synchronism with the timing of said single-phase clock pulses, and multi-phase gating means responsive to said single-phase clock pulses for connecting said plurality of arithmetic and control units to said a memory unit on a time-division basis.
References Cited (Backward Citations)
US3328566A
Cited
US3331954A
Cited
US3387273A
Cited
US3555516A
Cited
US3686490A
Cited
US3755784A
Cited
US3890600A
Cited
US3899667A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-30 | 1980-11-29 | 1981-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-30 | 1984-11-29 | 1985-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-30 | 1988-11-29 | 1989-05-31 | $7700.00 | Window Closed / Lapsed |