Method of performing a clear and wait operation with a single instruction

Claim 1

A method of performing a clear and wait operation with a single instruction in a processor having a plurality of programmable registers including a condition code register, by performing the following steps in response to a clear and wait instruction ANDing an immediate byte with contents of the condition code register so that the condition code register may be cleared if desired, the immediate byte being obtained from a preselected memory location; inhibiting a non-maskable interrupt during the ANDing of the immediate byte with the contents of the condition code register; stacking the plurality of programmable registers to save the state of the processor at time of performing the clear and wait operation; and waiting for an interrupt to occur so the interrupt can be directly serviced, and returning the processor to normal program execution after servicing the interrupt, thereby having performed a clear and wait operation with a single instruction.

Claim 2

A method of performing a clear and wait operation with a single instruction in a processor having a plurality of programmable registers including a condition code register, by performing the following steps in response to a clear and wait instruction ANDing an immediate byte with contents of the condition code register so that the condition code register may be cleared if desired, the immediate byte being obtained from a preselected memory location; inhibiting a non-maskable interrupt during the ANDing of the immediate byte with the contents of the condition code register; stacking the plurality of programmable registers to save the state of the processor at time of performing the clear and wait operation; and waiting for an interrupt to occur so the interrupt can be directly serviced, and returning the processor to normal program execution after servicing the interrupt, thereby having performed a clear and wait operation with a single instruction.

Claim 4

A method of performing a clear and wait operation with a single instruction in a microprocessor having a plurality of programmable registers including a condition code register, the microprocessor being capable of responding to a plurality of interrupts, wherein one of the plurality of interrupts is a non-maskable interrupt, the method comprising: recognizing a single clear and wait instruction and in response to the single clear and wait instruction performing the following steps, inhibiting the non-maskable interrupt temporarily, clearing at least one bit in the condition code register while the non-maskable interrupt is inhibited, stacking the plurality of programmable registers, and waiting for an interrupt to occur so that the interrupt can be serviced.

Claim 5

A method of performing a clear and wait operation with a single instruction in a microprocessor having a plurality of programmable registers including a condition code register, the microprocessor being capable of responding to a plurality of interrupts, wherein one of the plurality of interrupts is a non-maskable interrupt, the method comprising: recognizing a single clear and wait instruction and in response to the single clear and wait instruction performing the following steps, inhibiting the non-maskable interrupt temporarily, clearing at least one bit in the condition code register while the non-maskable interrupt is inhibited, stacking the plurality of programmable registers, and waiting for an interrupt to occur so that the interrupt can be serviced.

Claim 6

A method of performing a clear and wait function by a single instruction in a digital processor having a plurality of stackable registers, the method of performing the following steps in response to the single instruction comprising: ANDing contents from a storage location with contents of a condition code register to be able to clear any of the contents of the condition code register, the storage location being in a memory associated with the digital processor; stacking the plurality of stackable registers to save the state of the processor; and waiting for an interrupt to occur so that the interrupt can be serviced by the processor.

Claim 7

A method of performing a clear and wait function by a single instruction in a digital processor having a plurality of stackable registers, the method of performing the following steps in response to the single instruction comprising: ANDing contents from a storage location with contents of a condition code register to be able to clear any of the contents of the condition code register, the storage location being in a memory associated with the digital processor; stacking the plurality of stackable registers to save the state of the processor; and waiting for an interrupt to occur so that the interrupt can be serviced by the processor.