US4334268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer with branch on bit set/clear instructions
Assignee: Motorola Solutions Inc
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Filing: 1979-05-01
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Granted: 1982-06-08
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Expires: 1999-05-01
Abstract
Abstract A single-chip microcomputer comprises a central processor unit (100), a random access memory (110), a read only memory (120), internal timing circuitry including a timer counter (131), and three I/O data ports (140, 150, and 160). Included within the instruction set of the microcomputer are a branch on bit set instruction and a branch on bit clear instruction. The branch on bit set instruction is a three-byte instruction in which the first byte represents the op code including a designation of a particular bit to be examined, the second byte represents the address of a memory location in which the designated bit is to be examined, and the third byte represents an offset which when combined with the contents of the program counter designates a memory location to which a branch is to be taken if the designated bit is in fact set. For the branch on bit clear instruction, a branch is performed when the particular bit examined is determined not to be set. The branch on bit set and branch on bit clear instructions facilitate serial I/O operations by the microcomputer.
Inventors
- 👤 Joel F. Boney
- 👤 II Edward J. Rupp
- 👤 James S. Thomas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/324; G06F9/30003; G06F9/3005; G06F9/30058
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
135 words
In a data processing system comprising a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, a method of executing a conditional branch instruction, said instruction comprising an op code and a bit number, a first address portion designating a first storage location in said memory, and a second address portion designating a second storage location in said memory, said method comprising the steps of: fetching the data stored in said first storage location using said first address portion of said instruction; testing the state of the bit in the data fetched from said first storage location corresponding to said bit number; and branching to said second storage location using said second address portion of said instruction if said bit is in a predetermined state.
Claim 2
Dependent Claim
135 words
In a data processing system comprising a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, a method of executing a conditional branch instruction, said instruction comprising an op code and a bit number, a first address portion designating a first storage location in said memory, and a second address portion designating a second storage location in said memory, said method comprising the steps of: fetching the data stored in said first storage location using said first address portion of said instruction; testing the state of the bit in the data fetched from said first storage location corresponding to said bit number; and branching to said second storage location using said second address portion of said instruction if said bit is in a predetermined state.
Claim 3
Dependent Claim
144 words
In a data processing system comprising a memory for storing data and instructions in a plurality of storage locations therein, and a processor for executing instructions in said memory addressed by a program counter portion thereof, a method of executing a conditional branch instruction, said instruction comprising an op code, a bit number, an address portion designating a first storage location in said memory, and an offset, said method comprising the steps of: fetching the data stored in said first storage location using the address portion of said instruction; testing the state of the bit in the data fetched from said first storage location corresponding to said bit number; combining said offset with the contents of said processor program counter to provide a branch address; and branching to a second storage location using said branch address if said bit is in a predetermined state.
Claim 4
Dependent Claim
144 words
In a data processing system comprising a memory for storing data and instructions in a plurality of storage locations therein, and a processor for executing instructions in said memory addressed by a program counter portion thereof, a method of executing a conditional branch instruction, said instruction comprising an op code, a bit number, an address portion designating a first storage location in said memory, and an offset, said method comprising the steps of: fetching the data stored in said first storage location using the address portion of said instruction; testing the state of the bit in the data fetched from said first storage location corresponding to said bit number; combining said offset with the contents of said processor program counter to provide a branch address; and branching to a second storage location using said branch address if said bit is in a predetermined state.
Claim 5
Independent Claim
41 words
The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said memory includes a storage location for storing information relating to the operation of at least one I/O device coupled to said data processing system.
Claim 6
Independent Claim
23 words
The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said memory includes a random access memory.
Claim 7
Independent Claim
23 words
The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said memory includes a read only memory.
Claim 8
Independent Claim
27 words
The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said branching step is performed only if said bit is set.
Claim 9
Independent Claim
27 words
The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said branching step is performed only if said bit is clear.
Claim 10
Independent Claim
23 words
The method of executing a conditional branch instruction as recited in claims 1 or 2, wherein said data processing system is a microcomputer.
Claim 11
Dependent Claim
197 words
In a data processing system comprising a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, said processor including a program counter, an instruction decoding and control unit, and an arithmetic logic unit, the improvement wherein said memory includes a first storage location for storing a conditional branch instruction, said conditional branch instruction comprising an op code and a bit number, a first portion designating a second storage location in said memory, and a second portion designating an offset, wherein said instruction decoding and control unit, responsive to said op code and said first portion of said conditional branch instruction, locates said second storage location, wherein said arithmetic logic unit, responsive to said bit number, provides a control signal if the bit in said second storage location corresponding to said bit number is in a predetermined state, and wherein said arithmetic logic unit, responsive to said control signal, combines said offset with the contents of said program counter to provide a memory address, whereby if said bit is in said predetermined state a branch is made to the location in said memory specified by said memory address.
Claim 12
Dependent Claim
197 words
In a data processing system comprising a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, said processor including a program counter, an instruction decoding and control unit, and an arithmetic logic unit, the improvement wherein said memory includes a first storage location for storing a conditional branch instruction, said conditional branch instruction comprising an op code and a bit number, a first portion designating a second storage location in said memory, and a second portion designating an offset, wherein said instruction decoding and control unit, responsive to said op code and said first portion of said conditional branch instruction, locates said second storage location, wherein said arithmetic logic unit, responsive to said bit number, provides a control signal if the bit in said second storage location corresponding to said bit number is in a predetermined state, and wherein said arithmetic logic unit, responsive to said control signal, combines said offset with the contents of said program counter to provide a memory address, whereby if said bit is in said predetermined state a branch is made to the location in said memory specified by said memory address.
Claim 13
Dependent Claim
17 words
The data processing system as recited in claim 9, wherein said data processing system is a microcomputer.
Claim 14
Dependent Claim
203 words
In a data processing system comprising a single-chip integrated circuit microcomputer including a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, said processor including a program counter, an instruction decoding and control unit, and an arithmetic logic unit, the improvement wherein said memory includes a first storage location for storing a conditional branch instruction, said conditional branch instruction comprising an op code and a bit number, a first portion designating a second storage location in said memory, and a second portion designating an offset, wherein said instruction decoding and control unit, responsive to said op code and said first portion of said conditional branch instruction, locates said second storage location, wherein said arithmetic logic unit, responsive to said bit number, provides a control signal if the bit in said second storage location corresponding to said bit number is in a predetermined state, and wherein said arithmetic logic unit, responsive to said control signal, combines said offset with the contents of said program counter to provide a memory address, whereby if said bit is in said predetermined state, a branch is made to the location in said memory specified by said memory address.
Claim 15
Dependent Claim
203 words
In a data processing system comprising a single-chip integrated circuit microcomputer including a memory having a plurality of storage locations for storing data and instructions and a processor for executing such instructions, said processor including a program counter, an instruction decoding and control unit, and an arithmetic logic unit, the improvement wherein said memory includes a first storage location for storing a conditional branch instruction, said conditional branch instruction comprising an op code and a bit number, a first portion designating a second storage location in said memory, and a second portion designating an offset, wherein said instruction decoding and control unit, responsive to said op code and said first portion of said conditional branch instruction, locates said second storage location, wherein said arithmetic logic unit, responsive to said bit number, provides a control signal if the bit in said second storage location corresponding to said bit number is in a predetermined state, and wherein said arithmetic logic unit, responsive to said control signal, combines said offset with the contents of said program counter to provide a memory address, whereby if said bit is in said predetermined state, a branch is made to the location in said memory specified by said memory address.
Claim 16
Dependent Claim
37 words
The data processing system as recited in claims 9 or 11, wherein said memory includes a storage location for storing information relating to the operation of at least one I/O device coupled to said data processing system.
Claim 17
Dependent Claim
19 words
The data processing system as recited in claims 9 or 11, wherein said memory includes a random access memory.
Claim 18
Dependent Claim
19 words
The data processing system as recited in claims 9 or 11, wherein said memory includes a read only memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-07 | 1985-12-07 | 1986-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-07 | 1989-12-07 | 1990-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-07 | 1993-12-07 | 1994-06-08 | $7700.00 | Window Closed / Lapsed |