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Patent US4644192A successfully refreshed from Google Patents.
US4644192A
Expired / Lapsed
US
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Programmable array logic with shared product terms and J-K registered outputs
Assignee: Intersil Corp
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Filing: 1985-09-19
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Granted: 1987-02-17
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Expires: 2005-09-19
Abstract
Abstract A programmable logic circuit of the type known as a PAL (programmable array logic) incorporates a J-K register for each of the circuit outputs. The PAL includes a programmable array for generating products of selected input terms. The product terms available at the array outputs can be programmably allocated to either or both of the J and K inputs. The provision of isolating circuitry allows for simultaneous sharing of each product term by both the J and K inputs.
Inventors
- 👤 Barbara J. Fisher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:07
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A programmable logic circuit, comprising: an array having a plurality of inputs for receiving input terms and a plurality of outputs and means for combining selected ones of said input terms to form product terms at each of said array outputs; a J-K register having J and K inputs and at least one output; and logic means having inputs connected to the array outputs, and having first and second logic outputs connected to the J and K inputs respectively, for selectively connecting certain ones of said array outputs to either or both of the J and K inputs of said J-K register.
Claim 2
Dependent Claim
102 words
A programmable logic circuit, comprising: an array having a plurality of inputs for receiving input terms and a plurality of outputs and means for combining selected ones of said input terms to form product terms at each of said array outputs; a J-K register having J and K inputs and at least one output; and logic means having inputs connected to the array outputs, and having first and second logic outputs connected to the J and K inputs respectively, for selectively connecting certain ones of said array outputs to either or both of the J and K inputs of said J-K register.
Claim 3
Dependent Claim
40 words
A programmable logic circuit according to claim 1, wherein said means for selectively connecting certain ones of said array outputs to said J input comprises a programmable element serially connected to means for electrically isolating said J and K inputs.
Claim 4
Dependent Claim
42 words
A programmable logic circuit according to claim 2, wherein said isolation means includes a three-terminal device having a first terminal connected to said programmable element, a second terminal connected to a power source and a third terminal connected to said array output.
Claim 5
Dependent Claim
23 words
A programmable logic circuit according to claim 3, wherein said three-terminal device is a transistor and said third terminal is a control terminal.
Claim 6
Dependent Claim
40 words
A programmable logic circuit according to claim 1, wherein said means for selectively connecting certain ones of said array outputs to said K input comprises a programmable element serially connected to means for electrically isolating said J and K inputs.
Claim 7
Dependent Claim
42 words
A programmable logic circuit according to claim 5, wherein said isolation means includes a three-terminal device having a first terminal connected to said programmable element, a second terminal connected to a power source and a third terminal connected to said array output.
Claim 8
Dependent Claim
23 words
A programmable logic circuit according to claim 6, wherein said three-terminal device is a transistor and said third terminal is a control terminal.
Claim 9
Dependent Claim
20 words
A programmable logic circuit according to claim 1, further comprising means for converting the J-K register to a D register.
Claim 10
Dependent Claim
20 words
A programmable logic circuit according to claim 1, further comprising means for converting the J-K register to a toggle register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |