High-level CMOS driver circuit

Claim 2

A driver circuit, comprising: an input node having a first logic state and a second logic state, said first and second logic states represented by different voltages, an output node having capacitance to be charged when said input node goes from said first logic state to said second logic state, charging means, connected to a first voltage supply and having an output, responsive to said input node so that said charging means connects said first voltage supply to said output of said charging means in response to said input node going from said first logic state to said second logic state, a series transistor having a source-to-drain path connected between said output of said charging means and said output node, and having a gate coupled to said first voltage supply so that said source-to-drain path of said series transistor connects said output of said charging means to said output node, thereby causing said capacitance to be charged by said first voltage supply in response to said input node going from said first logic state to said second logic state, and means, coupled to said input node, for connecting a second voltage supply of magnitude greater than said first voltage supply to said output node in response to said input node going from said first logic state to said second logic state.

Claim 3

A circuit according to claim 1 wherein said charging means comprises an inverter comprising a first transistor and a second transistor, said first and second transistors each having a source-to-drain path, such source-to-drain paths being connected in series between a first voltage supply and ground, said inverter having an output at the juncture of such source-to-drain paths, said first and second transistors having opposite channel conductivity-type, and said first and second transistors each having a gate connected to said input node so that said output of said inverter is connected to said first voltage supply in response to said input node going from said first logic state to said second logic state.

Claim 4

A circuit according to claim 2 wherein said means for connecting said second voltage supply to said output node comprises: a third transistor having a source-to-drain path connected between said second voltage supply and said output node, and having a gate, and a first biasing means, responsive to said input node and connected to said gate of said third transistor, for biasing the gate of said third transistor so that said second voltage supply is connected to said output node in response to said input node going from said first logic state to said second logic state.

Claim 5

A circuit according to claim 3 wherein said first biasing means comprises a fourth transistor having a source-to-drain path connected between the gate of said third transistor and said input node, and having a gate coupled to said output of said inverter so that, in response to said input node going from said first logic state to said second logic state, said gate of said third transistor is connected to said input node thereby connecting said second voltage supply to said output node.

Claim 6

A circuit according to claim 3 further comprising a second bisting means, responsive to said input node and connected to said gate of said third transistor, for biasing the gate of said third transistor so that said second voltage supply is disconnected from said output node in response to said input node returning from said second logic state to said first logic state.

Claim 7

A circuit according to claim 5 wherein said source-to-drain path of said third transistor is made non-conductive when said gate of said third transistor is connected to said second voltage supply, and wherein said second biasing means comprises a fifth transistor having a source-to-drain path connected between the gate of said third transistor and said second voltage supply, and having a gate coupled to said output of said inverter so that, in response to said input node returning from said second logic state to said first logic state, said second voltage supply is connected to said gate of said third transistor, thereby causing said second voltage supply to be disconnected from said output node.

Claim 8

A circuit according to claim 6 further comprising a third biasing means, responsive to said input node and connected to said gate of said fifth transistor, for biasing said gate of said fifth transistor so that said source-to-drain path of said fifth transistor is made non-conductive in response to said input node going from said first logic state to said second logic state.

Claim 9

A driver circuit, comprising: an input node having a first logic state and a second logic state, said first and second logic states represented by different voltages, an output node having capacitance to be charged when said input node goes from said first logic state to said second logic state, charging means, connected to a first voltage supply and having an output, responsive to said input node so that said charging means connects said first voltage supply to said output of said charging means in response to said input node going from said first logic state to said second logic state, a series transistor having a source-to-drain path connected between said output of said charging means and said output node, and having a gate, means, coupled to said input node, for connecting a second voltage supply of magnitude greater than said first voltage supply to said output node in response to said input node going from said first logic state to said second logic state, and means, responsive to said input node and connected to said gate of said series transistor, for biasing said gate of said series transistor so that said output of said charging means is connected to said output node for a predetermined period of time after said input node goes from said first logic state to said second logic state and is disconnected after said predetermined period of time.

Claim 10

A driver circuit, comprising: an input node having a first logic state and a second logic state, said first and second logic states represented by different voltages, an output node having capacitance to be charged when said input node goes from said first logic state to said second logic state, charging means, connected to a first voltage supply and having an output, responsive to said input node so that said charging means connects said first voltage supply to said output of said charging means in response to said input node going from said first logic state to said second logic state, a series transistor having a source-to-drain path connected between said output of said charging means and said output node, and having a gate, means, coupled to said input node, for connecting a second voltage supply of magnitude greater than said first voltage supply to said output node in response to said input node going from said first logic state to said second logic state, and means, responsive to said input node and connected to said gate of said series transistor, for biasing said gate of said series transistor so that said output of said charging means is connected to said output node for a predetermined period of time after said input node goes from said first logic state to said second logic state and is disconnected after said predetermined period of time.

Claim 11

A circuit according to claim 8 further comprising means, connected between said biasing means and said gate of said series transistor, for isolating said gate of said series transistor from said biasing means so that the voltage at the gate of said series transistor reaches a voltage greater than the voltage of said first voltage supply during such time as said output of said charging means is connected to said output node, thereby allowing said first voltage supply to charge said capacitance until said voltage on said capacitance reaches a voltage greater than the voltage of said first voltage supply less one transistor threshold voltage drop.

Claim 12

A circuit to claim 8 wherein said charging means comprises a first inverter comprising a first transistor and a second transistor, said first and second transistors each having a source-to-drain path, such source-to-drain paths being connected in series between a first voltage supply and ground, said first inverter having an output at the juncture of said source-to-drain paths, said first and second transistors having opposite channel conductivity-type, and said first and second transistors each having a gate connected to said input node so that said output of said first inverter is connected to said first voltage supply in response to said input node going from said first logic state to said second logic state.

Claim 13

A circuit according to claim 10 wherein said biasing means comprises: a second inverter having a third transistor and a fourth transistor, said third and fourth transistors each having a source-to-drain path, such source-to-drain paths being connected in series between said first voltage supply and ground, said third and fourth transistors having opposite channel conductivity-type, said third and fourth transistors each having a gate, such gates connected to each other and coupled to said output of said charging means, and said second inverter having an output at the juncture of said source-to-drain paths, said output coupled to said gate of said series transistor so that, in response to said input node going from said first logic state to said second logic state, said gate of said series transistor is biased so that said output node is disconnected from said output of said first inverter after such time as said first voltage supply has charged said capacitance.

Claim 14

A circuit according to claim 11 further comprising a fifth transistor having a source-to-drain path connected between said gate of said series transistor and said output of said second inverter, and having a gate connected to said first voltage supply so that said gate of said series transistor reaches a voltage greater than the level of the first voltage supply during such time as said output of said first inverter is connected to said output node, thereby allowing said first voltage supply to charge said capacitance to a voltage greater than the level of said first voltage supply less one transistor threshold voltage drop.

Claim 15

A CMOS driver circuit, comprising: an input node receiving a low-level signal, an output node having significant capacitance to be charged when said low-level signal switches, a CMOS inverter with a P-channel transistor and an N-channel transistor, said transistors having source-to-drain paths connected in series between a first voltage supply and ground, and an output at the juncture of such source-to-drain paths, the gates of said transistors being connected to said input node. an output stage having first and second P-channel transistors, each having a source-to-drain path and a gate, and second voltage supply, the source-to-drain path of the first transistor connecting said second voltage supply to said output node, the gate of said first transistor being connected to a control node, the source-to-drain path of said second transistor connecting said second voltage supply to said control node, the gate of said second transistor being connected to said output node, a series transistor having a source-to-drain path and a gate, the source-to-drain path of said series transistor being connected between said output of the inverter and said output node, the gate of said series transistor being coupled to said first voltage supply, and a control transistor having source-to-drain path and a gate, the source-to-drain path of said control transistor connecting said control node to said input node, the gate of said control transistor being coupled to said output node.

Claim 16

A CMOS driver circuit, comprising: an input node receiving a low-level signal, an output node having significant capacitance to be charged when said low-level signal switches, a CMOS inverter with a P-channel transistor and an N-channel transistor, said transistors having source-to-drain paths connected in series between a first voltage supply and ground, and an output at the juncture of such source-to-drain paths, the gates of said transistors being connected to said input node. an output stage having first and second P-channel transistors, each having a source-to-drain path and a gate, and second voltage supply, the source-to-drain path of the first transistor connecting said second voltage supply to said output node, the gate of said first transistor being connected to a control node, the source-to-drain path of said second transistor connecting said second voltage supply to said control node, the gate of said second transistor being connected to said output node, a series transistor having a source-to-drain path and a gate, the source-to-drain path of said series transistor being connected between said output of the inverter and said output node, the gate of said series transistor being coupled to said first voltage supply, and a control transistor having source-to-drain path and a gate, the source-to-drain path of said control transistor connecting said control node to said input node, the gate of said control transistor being coupled to said output node.

Claim 17

A circuit according to claim 13 wherein said control transistor and said series transistor are both N-channel MOS transistors.

Claim 18

A circuit according to claim 13 wherein said second voltage supply is at least about one Vt above the voltage of the first voltage supply.

Claim 19

A circuit according to claim 15 wherein said driver circuit is constructed on a semiconductor integrated circuit chip.

Claim 20

A circuit according to claim 16 wherein said first voltage supply is connected to said chip from external to the chip, and said second voltage supply is generated on said chip from said first voltage supply.

Claim 21

A circuit according to claim 17 wherein said capacitance is charged from said first voltage supply for an initial period after said input signal goes from a high level to a low level, and then is charged from said second voltage supply for a final period until said output node reaches a voltage above the level of said first voltage supply.

Claim 22

A driver circuit, comprising: an input node which has one and another logic states represented by substantially different voltages, an output node having substantial capacitance to be charged when said input node goes from said one to said another logic state, an inverter with a first transistor and a second transistor, said transistors having source-to-drain paths connected in series between a first voltage supply and ground, said first and second transistors having opposite channel conductivity-type, and an output at the juncture of such source-to-drain paths, the gates of said transistors being connected to said input node, a series transistor having a source-to-drain path and a gate, the source-to-drain path of said series transistor being connected between said output of the inverter and said output node, and the gate of said series transistor coupled to said first voltage supply in such a manner as to charge said capacitance from said first voltage supply when said input node goes from said one to said another logic state, and high voltage charging means connecting said output node to a second voltage supply of magnitude higher than said first voltage supply, said charging means having a first input coupled to said output node and a second input coupled to said input node.

Claim 23

A driver circuit, comprising: an input node which has one and another logic states represented by substantially different voltages, an output node having substantial capacitance to be charged when said input node goes from said one to said another logic state, an inverter with a first transistor and a second transistor, said transistors having source-to-drain paths connected in series between a first voltage supply and ground, said first and second transistors having opposite channel conductivity-type, and an output at the juncture of such source-to-drain paths, the gates of said transistors being connected to said input node, a series transistor having a source-to-drain path and a gate, the source-to-drain path of said series transistor being connected between said output of the inverter and said output node, and the gate of said series transistor coupled to said first voltage supply in such a manner as to charge said capacitance from said first voltage supply when said input node goes from said one to said another logic state, and high voltage charging means connecting said output node to a second voltage supply of magnitude higher than said first voltage supply, said charging means having a first input coupled to said output node and a second input coupled to said input node.

Claim 24

A circuit according to claim 19 wherein said charging means includes third and fourth transistors, each having a source-to-drain path and a gate, the source-to-drain path of the third transistor connecting said second voltage supply to said output node, the source-to-drain path of said fourth transistor connecting said second voltage supply to the gate of said third transistor, said gate of the third transistor being coupled to said input node by a coupling means, and said gate of the fourth transistor being coupled to said output node.

Claim 25

A circuit according to claim 20 wherein said coupling means is controlled by said output node.

Claim 26

A circuit according to claim 21 wherein said coupling means is a fifth transistor having its gate coupled to said output node and having a source-to-drain path connected between said gate of the third transistor and said input node.

Claim 27

A circuit according to claim 19 wherein said gate of said series transistor is coupled to said voltage supply.

Claim 28

A circuit according to claim 19 wherein said first transistor is P-channel, and said second transistor and said series transistor are N-channel.

Claim 29

A circuit according to claim 23 wherein said third and fourth transistors are of the same type as said first transistor.

Claim 30

A circuit according to claim 25 wherein said first, third and fourth transistors are P-channel and said second, series, and fifth transistors are N-channel.